From patchwork Thu May 12 17:24:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= X-Patchwork-Id: 9084801 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 323FABF29F for ; Thu, 12 May 2016 17:24:51 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 68C9020220 for ; Thu, 12 May 2016 17:24:50 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A21F3200EC for ; Thu, 12 May 2016 17:24:49 +0000 (UTC) Received: from localhost ([::1]:58956 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b0uLw-00047w-Rq for patchwork-qemu-devel@patchwork.kernel.org; Thu, 12 May 2016 13:24:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42365) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b0uLp-00046P-NV for qemu-devel@nongnu.org; Thu, 12 May 2016 13:24:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b0uLl-0005XQ-DZ for qemu-devel@nongnu.org; Thu, 12 May 2016 13:24:40 -0400 Received: from mx1.redhat.com ([209.132.183.28]:60982) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b0uLl-0005Wy-4A for qemu-devel@nongnu.org; Thu, 12 May 2016 13:24:37 -0400 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7502B15555; Thu, 12 May 2016 17:24:36 +0000 (UTC) Received: from potion (dhcp-1-215.brq.redhat.com [10.34.1.215]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with SMTP id u4CHOYAk005205; Thu, 12 May 2016 13:24:34 -0400 Received: by potion (sSMTP sendmail emulation); Thu, 12 May 2016 19:24:33 +0200 From: =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= To: qemu-devel@nongnu.org Date: Thu, 12 May 2016 19:24:26 +0200 Message-Id: <1463073866-28802-1-git-send-email-rkrcmar@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Thu, 12 May 2016 17:24:36 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v3] target-i386: implement CPUID[0xB] (Extended Topology Enumeration) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Eduardo Habkost , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP I looked at a dozen Intel CPU that have this CPUID and all of them always had Core offset as 1 (a wasted bit when hyperthreading is disabled) and Package offset at least 4 (wasted bits at <= 4 cores). QEMU uses more compact IDs and it doesn't make much sense to change it now. I keep the SMT and Core sub-leaves even if there is just one thread/core; it makes the code simpler and there should be no harm. Signed-off-by: Radim Kr?má? Reviewed-by: Igor Mammedov Reviewed-by: Eduardo Habkost --- This patch depends on Igor's "pc: add 2.7 machine". v2: * assert *eax instead of silently masking [Eduardo] * backward compatibility through CPU property [Eduardo] v3: use count instead of *ecx to access leaves, hardware does include/hw/i386/pc.h | 7 ++++++- target-i386/cpu-qom.h | 3 +++ target-i386/cpu.c | 32 ++++++++++++++++++++++++++++++++ target-i386/cpu.h | 5 +++++ 4 files changed, 46 insertions(+), 1 deletion(-) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index a91e8e734f07..e294fa945d30 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -361,7 +361,12 @@ int e820_get_num_entries(void); bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); #define PC_COMPAT_2_6 \ - HW_COMPAT_2_6 + HW_COMPAT_2_6 \ + {\ + .driver = TYPE_X86_CPU,\ + .property = "cpuid-0xb",\ + .value = "off",\ + }, #define PC_COMPAT_2_5 \ PC_COMPAT_2_6 \ diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h index cb750176c0c0..b84963d42463 100644 --- a/target-i386/cpu-qom.h +++ b/target-i386/cpu-qom.h @@ -115,6 +115,9 @@ typedef struct X86CPU { */ bool enable_pmu; + /* Compatibility bits for old machine types. */ + bool enable_cpuid_0xb; + /* in order to simplify APIC support, we leave this pointer to the user */ struct DeviceState *apic_state; diff --git a/target-i386/cpu.c b/target-i386/cpu.c index d0b5b691563c..a17ef191c270 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -35,6 +35,7 @@ #include "sysemu/arch_init.h" #include "hw/hw.h" +#include "hw/i386/topology.h" #if defined(CONFIG_KVM) #include #endif @@ -2460,6 +2461,36 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *edx = 0; } break; + case 0xB: + /* Extended Topology Enumeration Leaf */ + if (!cpu->enable_cpuid_0xb) { + *eax = *ebx = *ecx = *edx = 0; + break; + } + + *ecx = count & 0xff; + *edx = cpu->apic_id; + + switch (count) { + case 0: + *eax = apicid_core_offset(smp_cores, smp_threads); + *ebx = smp_threads; + *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; + break; + case 1: + *eax = apicid_pkg_offset(smp_cores, smp_threads); + *ebx = smp_cores * smp_threads; + *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; + break; + default: + *eax = 0; + *ebx = 0; + *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; + } + + assert(!(*eax & ~0x1f)); + *ebx &= 0xffff; /* The count doesn't need to be reliable. */ + break; case 0xD: { KVMState *s = cs->kvm_state; uint64_t ena_mask; @@ -3221,6 +3252,7 @@ static Property x86_cpu_properties[] = { DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0), DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0), DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id), + DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), DEFINE_PROP_END_OF_LIST() }; diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 732eb6d7ec79..b460c2debc1c 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -635,6 +635,11 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ +/* CPUID[0xB].ECX level types */ +#define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) +#define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) +#define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) + #ifndef HYPERV_SPINLOCK_NEVER_RETRY #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF #endif