From patchwork Sat May 14 23:40:40 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Gang X-Patchwork-Id: 9095691 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8432FBF29F for ; Sat, 14 May 2016 23:46:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CD7F920272 for ; Sat, 14 May 2016 23:46:49 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 06FA32026F for ; Sat, 14 May 2016 23:46:49 +0000 (UTC) Received: from localhost ([::1]:39191 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b1jGi-0002LW-Bs for patchwork-qemu-devel@patchwork.kernel.org; Sat, 14 May 2016 19:46:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39238) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b1jGc-0002KX-Vn for qemu-devel@nongnu.org; Sat, 14 May 2016 19:46:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b1jGZ-0000lU-JO for qemu-devel@nongnu.org; Sat, 14 May 2016 19:46:42 -0400 Received: from out4433.biz.mail.alibaba.com ([47.88.44.33]:26333) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b1jGZ-0000lD-6O for qemu-devel@nongnu.org; Sat, 14 May 2016 19:46:39 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07925177|-1; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03281; MF=chengang@emindsoft.com.cn; NM=1; PH=DU; RN=9; RT=9; SR=0; TI=SMTPD_----4ooABWA_1463269267; Received: from localhost.localdomain(mailfrom:chengang@emindsoft.com.cn ip:223.72.89.121) by smtp.aliyun-inc.com(10.147.40.2); Sun, 15 May 2016 07:41:15 +0800 From: chengang@emindsoft.com.cn To: rth@twiddle.net, peter.maydell@linaro.org, cmetcalf@ezchip.com, laurent@vivier.eu Date: Sun, 15 May 2016 07:40:40 +0800 Message-Id: <1463269244-3391-2-git-send-email-chengang@emindsoft.com.cn> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1463269244-3391-1-git-send-email-chengang@emindsoft.com.cn> References: <1463269244-3391-1-git-send-email-chengang@emindsoft.com.cn> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 47.88.44.33 Subject: [Qemu-devel] [PATCH v6 1/5] fpu: softfloat: Add normalize_roundpack_float[32|64] functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: chenwei@emindsoft.com.cn, riku.voipio@iki.fi, Chen Gang , qemu-devel@nongnu.org, Chen Gang Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Chen Gang normalize_roundpack_float32 is based on (u)int32_to_float32 function to support float32 packing. normalize_roundpack_float64 is the special case of roundAndPackFloat64. Signed-off-by: Chen Gang --- fpu/softfloat.c | 65 +++++++++++++++++++++++++++++++++++++++++++++++++ include/fpu/softfloat.h | 15 ++++++++++++ 2 files changed, 80 insertions(+) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 166c48e..ecdfa7f 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1516,6 +1516,16 @@ float64 uint64_to_float64(uint64_t a, float_status *status) return roundAndPackFloat64(0, exp - shiftcount, a, status); } +/* + * The mantissa contents the hide bit (60-bit), which is the special case of + * roundAndPackFloat64(). + */ +float64 normalize_roundpack_float64(flag sign, int_fast16_t exp, uint64_t sig, + float_status *status) +{ + return roundAndPackFloat64(sign, exp - 1, sig << 3, status); +} + /*---------------------------------------------------------------------------- | Returns the result of converting the 64-bit unsigned integer `a' | to the quadruple-precision floating-point format. The conversion is performed @@ -7090,6 +7100,61 @@ float64 uint32_to_float64(uint32_t a, float_status *status) return int64_to_float64(a, status); } +/* + * The mantissa contents the hide bit, e.g. exp: 0x9e with sig: 1 means 1.0f. + * + * It references from int32_to_float32() and uint32_to_float32() + */ +float32 normalize_roundpack_float32(flag sign, int_fast16_t exp, uint32_t sig, + float_status *status) +{ + uint64_t absa = sig; + int8_t scount; + + if (exp >= 0xff) { + return packFloat32(sign, 0xFF, 0); + } else if (exp <= 0) { + shift32RightJamming(sig, 0 - exp, &sig); + return packFloat32(sign, 0, sig); + } + + if (sign) { + if (sig & 0x7FFFFFFF) { + return normalizeRoundAndPackFloat32(1, exp - 2, sig, status); + } + if (sig) { + return packFloat32(1, exp, 0); + } else { + return float32_zero; + } + } + + if (!sig) { + return float32_zero; + } + + scount = countLeadingZeros64(absa) - 40; + if (scount >= 0) { + exp -= 7 + scount + 2; + if (exp <= 0) { + return packFloat32(0, 0, absa); + } + return packFloat32(0, exp, absa << scount); + } + + scount += 7; + exp -= scount + 2; + if (exp <= 0) { + return packFloat32(0, 0, absa); + } + if (scount < 0) { + shift64RightJamming(absa, 0 - scount, &absa); + } else { + absa <<= scount; + } + return roundAndPackFloat32(0, exp, absa, status); +} + uint32_t float32_to_uint32(float32 a, float_status *status) { int64_t v; diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index c937062..d4246a1 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -409,6 +409,14 @@ int float32_is_signaling_nan( float32 ); float32 float32_maybe_silence_nan( float32 ); float32 float32_scalbn(float32, int, float_status *status); +/* + * The mantissa contents the hide bit, e.g. exp: 0x9e with sig: 1 means 1.0f. + * + * It references from int32_to_float32() and uint32_to_float32() + */ +float32 normalize_roundpack_float32(flag sign, int_fast16_t exp, uint32_t sig, + float_status *status); + static inline float32 float32_abs(float32 a) { /* Note that abs does *not* handle NaN specially, nor does @@ -521,6 +529,13 @@ int float64_is_signaling_nan( float64 ); float64 float64_maybe_silence_nan( float64 ); float64 float64_scalbn(float64, int, float_status *status); +/* + * The mantissa contents the hide bit (60-bit), which is the special case of + * roundAndPackFloat64(). + */ +float64 normalize_roundpack_float64(flag sign, int_fast16_t exp, uint64_t sig, + float_status *status); + static inline float64 float64_abs(float64 a) { /* Note that abs does *not* handle NaN specially, nor does