From patchwork Sun May 15 13:49:36 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leonid Bloch X-Patchwork-Id: 9096371 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B5CE0BF29F for ; Sun, 15 May 2016 13:50:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DAC8B202A1 for ; Sun, 15 May 2016 13:50:32 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E7B03202AE for ; Sun, 15 May 2016 13:50:31 +0000 (UTC) Received: from localhost ([::1]:40397 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b1wRD-0007JS-6V for patchwork-qemu-devel@patchwork.kernel.org; Sun, 15 May 2016 09:50:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54148) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b1wQy-0007DH-6g for qemu-devel@nongnu.org; Sun, 15 May 2016 09:50:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b1wQv-0007VI-MF for qemu-devel@nongnu.org; Sun, 15 May 2016 09:50:15 -0400 Received: from mail-wm0-x233.google.com ([2a00:1450:400c:c09::233]:38908) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b1wQv-0007VD-CN for qemu-devel@nongnu.org; Sun, 15 May 2016 09:50:13 -0400 Received: by mail-wm0-x233.google.com with SMTP id g17so98334976wme.1 for ; Sun, 15 May 2016 06:50:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ravellosystems-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7x/OlkIgPAA3ihoPdnCjojweOj+wkLfXYPgs+lupNGo=; b=BrBNQpR+YyjjcRKKoRDanx5cY+kqgQmAUcwTrycBUT28zMs0N/DA6gqUMn4ypkzrem 2bF3BAxmksGALAUmfgtZrDIXNX6GOlpp/SZvSVIF79PoAZ4zJp6Na3H9/x4ZfLephVeu VhhIVznDlsWTUahINJB6BSBN9mREW+iWatDM5appLD/O72UNZNoIdeD0KNNqXfkNm0z3 uXXsbKB6JLnw/9PtCQUgfqgRPpimumdNeMPQ764Ut3gF/f2Git5W+NYEMi4gQ98oVVF3 8GyVAl/nHOHHVQmTPRVNSYN7VVDkZgcuHkiVsTMFL5/RvBA+MMLN7BA+Eh/kknHS6YKu 6Nsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7x/OlkIgPAA3ihoPdnCjojweOj+wkLfXYPgs+lupNGo=; b=Zqfwxd+Rt9Ws2yFytgwY0VM39gjp3ErQ7O4Aq3Jh6RGKVTYgXqzf6ldbapf+Hzis27 ALpc8i3XClHz3+4kWyPCo79dP9+Oy1f0QQEa2saaT7UoJtxm+G54+arBohN5BVkZtsp5 dApvjg+cMrLdNUkTK9NNsjZQRPrmAYg4vH5uZp0MVUNDE5s3w7ghD2UbnkGplG6Cp2wH Hs9foL64D3UdKs50OpEPOFBsCOvqvlkxFdpLW/XdUcboCr8awjItV67fxNhRzYFqWAs+ W/AWkN/f6HLoxvGoXsqWH5nJmfnkhxZhoF7ju9xrzxrv4p2mppJt138GiCMC0m/5L+sD UZDw== X-Gm-Message-State: AOPr4FWzIAYj5x912NDV8+6UBWTAUUPCMNN7j+Wehoqmgx4IopxEf5meT4r+8sWcQOMMYgey X-Received: by 10.194.87.195 with SMTP id ba3mr27849879wjb.80.1463320212680; Sun, 15 May 2016 06:50:12 -0700 (PDT) Received: from bark.daynix ([5.102.236.99]) by smtp.gmail.com with ESMTPSA id c4sm28742403wjm.24.2016.05.15.06.50.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 15 May 2016 06:50:11 -0700 (PDT) From: Leonid Bloch To: qemu-devel@nongnu.org Date: Sun, 15 May 2016 16:49:36 +0300 Message-Id: <1463320189-14108-4-git-send-email-leonid.bloch@ravellosystems.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1463320189-14108-1-git-send-email-leonid.bloch@ravellosystems.com> References: <1463320189-14108-1-git-send-email-leonid.bloch@ravellosystems.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::233 Subject: [Qemu-devel] [PATCH v5 03/16] pcie: Add support for PCIe CAP v1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dmitry Fleytman , Jason Wang , Leonid Bloch , Shmulik Ladkani , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dmitry Fleytman Added support for PCIe CAP v1, while reusing some of the existing v2 infrastructure. Signed-off-by: Dmitry Fleytman Signed-off-by: Leonid Bloch --- hw/pci/pcie.c | 84 ++++++++++++++++++++++++++++++++++++---------- include/hw/pci/pcie.h | 4 +++ include/hw/pci/pcie_regs.h | 5 +-- 3 files changed, 73 insertions(+), 20 deletions(-) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 728386a..24cfc3b 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -43,26 +43,15 @@ /*************************************************************************** * pci express capability helper functions */ -int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port) -{ - int pos; - uint8_t *exp_cap; - - assert(pci_is_express(dev)); - - pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, - PCI_EXP_VER2_SIZEOF); - if (pos < 0) { - return pos; - } - dev->exp.exp_cap = pos; - exp_cap = dev->config + pos; +static void +pcie_cap_v1_fill(uint8_t *exp_cap, uint8_t port, uint8_t type, uint8_t version) +{ /* capability register - interrupt message number defaults to 0 */ + interrupt message number defaults to 0 */ pci_set_word(exp_cap + PCI_EXP_FLAGS, ((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) | - PCI_EXP_FLAGS_VER2); + version); /* device capability register * table 7-12: @@ -81,7 +70,27 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port) pci_set_word(exp_cap + PCI_EXP_LNKSTA, PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25 |PCI_EXP_LNKSTA_DLLLA); +} + +int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port) +{ + /* PCIe cap v2 init */ + int pos; + uint8_t *exp_cap; + + assert(pci_is_express(dev)); + + pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, PCI_EXP_VER2_SIZEOF); + if (pos < 0) { + return pos; + } + dev->exp.exp_cap = pos; + exp_cap = dev->config + pos; + + /* Filling values common with v1 */ + pcie_cap_v1_fill(exp_cap, port, type, PCI_EXP_FLAGS_VER2); + /* Filling v2 specific values */ pci_set_long(exp_cap + PCI_EXP_DEVCAP2, PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP); @@ -89,7 +98,29 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port) return pos; } -int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset) +int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type, + uint8_t port) +{ + /* PCIe cap v1 init */ + int pos; + uint8_t *exp_cap; + + assert(pci_is_express(dev)); + + pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, PCI_EXP_VER1_SIZEOF); + if (pos < 0) { + return pos; + } + dev->exp.exp_cap = pos; + exp_cap = dev->config + pos; + + pcie_cap_v1_fill(exp_cap, port, type, PCI_EXP_FLAGS_VER1); + + return pos; +} + +static int +pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t offset, uint8_t cap_size) { uint8_t type = PCI_EXP_TYPE_ENDPOINT; @@ -102,7 +133,19 @@ int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset) type = PCI_EXP_TYPE_RC_END; } - return pcie_cap_init(dev, offset, type, 0); + return (cap_size == PCI_EXP_VER1_SIZEOF) + ? pcie_cap_v1_init(dev, offset, type, 0) + : pcie_cap_init(dev, offset, type, 0); +} + +int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset) +{ + return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER2_SIZEOF); +} + +int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset) +{ + return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER1_SIZEOF); } void pcie_cap_exit(PCIDevice *dev) @@ -110,6 +153,11 @@ void pcie_cap_exit(PCIDevice *dev) pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF); } +void pcie_cap_v1_exit(PCIDevice *dev) +{ + pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER1_SIZEOF); +} + uint8_t pcie_cap_get_type(const PCIDevice *dev) { uint32_t pos = dev->exp.exp_cap; diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index b48a7a2..cbbf0c5 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -80,8 +80,12 @@ struct PCIExpressDevice { /* PCI express capability helper functions */ int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port); +int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, + uint8_t type, uint8_t port); int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset); void pcie_cap_exit(PCIDevice *dev); +int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset); +void pcie_cap_v1_exit(PCIDevice *dev); uint8_t pcie_cap_get_type(const PCIDevice *dev); void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector); uint8_t pcie_cap_flags_get_vector(PCIDevice *dev); diff --git a/include/hw/pci/pcie_regs.h b/include/hw/pci/pcie_regs.h index 6a28b33..a95522a 100644 --- a/include/hw/pci/pcie_regs.h +++ b/include/hw/pci/pcie_regs.h @@ -11,6 +11,7 @@ /* express capability */ +#define PCI_EXP_VER1_SIZEOF 0x14 /* express capability of ver. 1 */ #define PCI_EXP_VER2_SIZEOF 0x3c /* express capability of ver. 2 */ #define PCI_EXT_CAP_VER_SHIFT 16 #define PCI_EXT_CAP_NEXT_SHIFT 20 @@ -26,11 +27,11 @@ (((x) + PCI_EXT_CAP_ALIGN - 1) & ~(PCI_EXT_CAP_ALIGN - 1)) /* PCI_EXP_FLAGS */ -#define PCI_EXP_FLAGS_VER2 2 /* for now, supports only ver. 2 */ +#define PCI_EXP_FLAGS_VER1 1 +#define PCI_EXP_FLAGS_VER2 2 #define PCI_EXP_FLAGS_IRQ_SHIFT ctz32(PCI_EXP_FLAGS_IRQ) #define PCI_EXP_FLAGS_TYPE_SHIFT ctz32(PCI_EXP_FLAGS_TYPE) - /* PCI_EXP_LINK{CAP, STA} */ /* link speed */ #define PCI_EXP_LNK_LS_25 1