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[78.12.252.58]) by smtp.gmail.com with ESMTPSA id lf9sm34386875wjc.44.2016.05.16.08.36.37 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 May 2016 08:36:38 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Mon, 16 May 2016 17:35:44 +0200 Message-Id: <1463412982-6681-13-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1463412982-6681-1-git-send-email-pbonzini@redhat.com> References: <1463412982-6681-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [PATCH 12/50] target-mips: make cpu-qom.h not target specific X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Make MIPSCPU an opaque type within cpu-qom.h, and move all definitions of private methods, as well as all type definitions that require knowledge of the layout to cpu.h. This helps making files independent of NEED_CPU_H if they only need to pass around CPU pointers. Signed-off-by: Paolo Bonzini --- target-mips/cpu-qom.h | 37 +------------------------------------ target-mips/cpu.h | 38 +++++++++++++++++++++++++++++++++++++- 2 files changed, 38 insertions(+), 37 deletions(-) diff --git a/target-mips/cpu-qom.h b/target-mips/cpu-qom.h index 4d6f9de..3f5bf23 100644 --- a/target-mips/cpu-qom.h +++ b/target-mips/cpu-qom.h @@ -51,41 +51,6 @@ typedef struct MIPSCPUClass { void (*parent_reset)(CPUState *cpu); } MIPSCPUClass; -/** - * MIPSCPU: - * @env: #CPUMIPSState - * - * A MIPS CPU. - */ -typedef struct MIPSCPU { - /*< private >*/ - CPUState parent_obj; - /*< public >*/ - - CPUMIPSState env; -} MIPSCPU; - -static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env) -{ - return container_of(env, MIPSCPU, env); -} - -#define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e)) - -#define ENV_OFFSET offsetof(MIPSCPU, env) - -#ifndef CONFIG_USER_ONLY -extern const struct VMStateDescription vmstate_mips_cpu; -#endif - -void mips_cpu_do_interrupt(CPUState *cpu); -bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); -void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, - int flags); -hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); -int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - int is_write, int is_user, uintptr_t retaddr); +typedef struct MIPSCPU MIPSCPU; #endif diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 866924d..078fabc 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -8,6 +8,7 @@ #define CPUArchState struct CPUMIPSState #include "qemu-common.h" +#include "cpu-qom.h" #include "mips-defs.h" #include "exec/cpu-defs.h" #include "fpu/softfloat.h" @@ -615,7 +616,42 @@ struct CPUMIPSState { MemoryRegion *itc_tag; /* ITC Configuration Tags */ }; -#include "cpu-qom.h" +/** + * MIPSCPU: + * @env: #CPUMIPSState + * + * A MIPS CPU. + */ +struct MIPSCPU { + /*< private >*/ + CPUState parent_obj; + /*< public >*/ + + CPUMIPSState env; +}; + +static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env) +{ + return container_of(env, MIPSCPU, env); +} + +#define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e)) + +#define ENV_OFFSET offsetof(MIPSCPU, env) + +#ifndef CONFIG_USER_ONLY +extern const struct VMStateDescription vmstate_mips_cpu; +#endif + +void mips_cpu_do_interrupt(CPUState *cpu); +bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); +void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, + int flags); +hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, + int is_write, int is_user, uintptr_t retaddr); #if !defined(CONFIG_USER_ONLY) int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,