From patchwork Tue May 17 13:07:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Hajnoczi X-Patchwork-Id: 9112121 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0147ABF29F for ; Tue, 17 May 2016 13:07:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 444942022D for ; Tue, 17 May 2016 13:07:25 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 40C1E2010E for ; Tue, 17 May 2016 13:07:24 +0000 (UTC) Received: from localhost ([::1]:50201 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b2eiZ-00051v-C9 for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 May 2016 09:07:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59856) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b2eiN-0004sz-BP for qemu-devel@nongnu.org; Tue, 17 May 2016 09:07:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b2eiK-0007kQ-Uu for qemu-devel@nongnu.org; Tue, 17 May 2016 09:07:10 -0400 Received: from mx1.redhat.com ([209.132.183.28]:40121) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b2eiK-0007je-NS for qemu-devel@nongnu.org; Tue, 17 May 2016 09:07:08 -0400 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 5E53D552E6; Tue, 17 May 2016 13:07:08 +0000 (UTC) Received: from localhost (ovpn-112-43.ams2.redhat.com [10.36.112.43]) by int-mx14.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u4HD75LF027538; Tue, 17 May 2016 09:07:07 -0400 From: Stefan Hajnoczi To: Date: Tue, 17 May 2016 06:07:01 -0700 Message-Id: <1463490421-20032-2-git-send-email-stefanha@redhat.com> In-Reply-To: <1463490421-20032-1-git-send-email-stefanha@redhat.com> References: <1463490421-20032-1-git-send-email-stefanha@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.27 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Tue, 17 May 2016 13:07:08 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 1/1] hw/intc/arm_gic: add tracepoints X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Hollis Blanchard , Stefan Hajnoczi Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Hollis Blanchard These are obviously critical to understanding interrupt delivery: gic_enable_irq gic_disable_irq gic_set_irq (inbound irq from device models) gic_update_set_irq (outbound irq to CPU) gic_acknowledge_irq The only one that I think might raise eyebrows is gic_update_bestirq, but I've (sadly) debugged problems that ended up being caused by unexpected priorities. Knowing that the GIC has an irq ready, but doesn't deliver to the CPU due to priority, has also proven important. Signed-off-by: Hollis Blanchard Message-id: 1461252281-22399-1-git-send-email-hollis_blanchard@mentor.com Signed-off-by: Stefan Hajnoczi --- hw/intc/arm_gic.c | 12 ++++++++++++ trace-events | 8 ++++++++ 2 files changed, 20 insertions(+) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index f551241..5ee79b8 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -23,6 +23,7 @@ #include "gic_internal.h" #include "qapi/error.h" #include "qom/cpu.h" +#include "trace.h" //#define DEBUG_GIC @@ -93,6 +94,11 @@ void gic_update(GICState *s) } } + if (best_irq != 1023) { + trace_gic_update_bestirq(cpu, best_irq, best_prio, + s->priority_mask[cpu], s->running_priority[cpu]); + } + irq_level = fiq_level = 0; if (best_prio < s->priority_mask[cpu]) { @@ -106,10 +112,12 @@ void gic_update(GICState *s) DPRINTF("Raised pending FIQ %d (cpu %d)\n", best_irq, cpu); fiq_level = 1; + trace_gic_update_set_irq(cpu, "fiq", fiq_level); } else { DPRINTF("Raised pending IRQ %d (cpu %d)\n", best_irq, cpu); irq_level = 1; + trace_gic_update_set_irq(cpu, "irq", irq_level); } } } @@ -197,6 +205,7 @@ static void gic_set_irq(void *opaque, int irq, int level) } else { gic_set_irq_generic(s, irq, level, cm, target); } + trace_gic_set_irq(irq, level, cm, target); gic_update(s); } @@ -332,6 +341,7 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) * is in the wrong group. */ irq = gic_get_current_pending_irq(s, cpu, attrs); + trace_gic_acknowledge_irq(cpu, irq); if (irq >= GIC_MAXIRQ) { DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq); @@ -853,6 +863,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, if (!GIC_TEST_ENABLED(irq + i, cm)) { DPRINTF("Enabled IRQ %d\n", irq + i); + trace_gic_enable_irq(irq + i); } GIC_SET_ENABLED(irq + i, cm); /* If a raised level triggered IRQ enabled then mark @@ -879,6 +890,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, if (GIC_TEST_ENABLED(irq + i, cm)) { DPRINTF("Disabled IRQ %d\n", irq + i); + trace_gic_disable_irq(irq + i); } GIC_CLEAR_ENABLED(irq + i, cm); } diff --git a/trace-events b/trace-events index 4fce005..e35b80e 100644 --- a/trace-events +++ b/trace-events @@ -1908,3 +1908,11 @@ aspeed_vic_update_fiq(int flags) "Raising FIQ: %d" aspeed_vic_update_irq(int flags) "Raising IRQ: %d" aspeed_vic_read(uint64_t offset, unsigned size, uint32_t value) "From 0x%" PRIx64 " of size %u: 0x%" PRIx32 aspeed_vic_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 + +# hw/intc/arm_gic.c +gic_enable_irq(int irq) "irq %d enabled" +gic_disable_irq(int irq) "irq %d disabled" +gic_set_irq(int irq, int level, int cpumask, int target) "irq %d level %d cpumask 0x%x target 0x%x" +gic_update_bestirq(int cpu, int irq, int prio, int priority_mask, int running_priority) "cpu %d irq %d priority %d cpu priority mask %d cpu running priority %d" +gic_update_set_irq(int cpu, const char *name, int level) "cpu[%d]: %s = %d" +gic_acknowledge_irq(int cpu, int irq) "cpu %d acknowledged irq %d"