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Sun, 22 May 2016 03:22:40 -0700 (PDT) Received: from debian.flybox.orange ([154.122.6.169]) by smtp.googlemail.com with ESMTPSA id u4sm29189515wjz.4.2016.05.22.03.22.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 22 May 2016 03:22:39 -0700 (PDT) From: David Kiarie To: qemu-devel@nongnu.org Date: Sun, 22 May 2016 13:21:54 +0300 Message-Id: <1463912514-12658-5-git-send-email-davidkiarie4@gmail.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1463912514-12658-1-git-send-email-davidkiarie4@gmail.com> References: <1463912514-12658-1-git-send-email-davidkiarie4@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [V11 4/4] hw/pci-host: Emulate AMD IOMMU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, peterx@redhat.com, valentine.sinitsyn@gmail.com, jan.kiszka@web.de, marcel@redhat.com, David Kiarie Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add AMD IOMMU emulation support to q35 chipset Signed-off-by: David Kiarie --- hw/pci-host/q35.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 70f897e..26fea0e 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -32,6 +32,7 @@ #include "hw/pci-host/q35.h" #include "qapi/error.h" #include "qapi/visitor.h" +#include "hw/i386/amd_iommu.h" /**************************************************************************** * Q35 host @@ -448,6 +449,19 @@ static void mch_init_dmar(MCHPCIState *mch) pci_setup_iommu(pci_bus, q35_host_dma_iommu, mch->iommu); } +static void mch_init_amdvi(MCHPCIState *mch) +{ + AMDVIState *iommu_state; + PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(mch))); + PCIDevice *iommu; + + iommu = pci_create_simple(bus, 0x20, TYPE_AMD_IOMMU_DEVICE); + + iommu_state = AMD_IOMMU_DEVICE(iommu); + + pci_setup_iommu(bus, bridge_host_amdvi, iommu_state); +} + static void mch_realize(PCIDevice *d, Error **errp) { int i; @@ -506,9 +520,14 @@ static void mch_realize(PCIDevice *d, Error **errp) mch->pci_address_space, &mch->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); } - /* Intel IOMMU (VT-d) */ - if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) { - mch_init_dmar(mch); + + MachineState *machine = MACHINE(qdev_get_machine()); + if (machine->iommu) { + if (machine->iommu_type == TYPE_AMD) { + mch_init_amdvi(mch); + } else { + mch_init_dmar(mch); + } } }