@@ -8052,9 +8052,11 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
gen_clrex(s);
return;
case 4: /* dsb */
+ ARCH(7);
+ return;
case 5: /* dmb */
ARCH(7);
- /* We don't emulate caches so these are a no-op. */
+ tcg_gen_fence();
return;
case 6: /* isb */
/* We need to break the TB after this insn to execute
@@ -10402,8 +10404,9 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
gen_clrex(s);
break;
case 4: /* dsb */
+ break;
case 5: /* dmb */
- /* These execute as NOPs. */
+ tcg_gen_fence();
break;
case 6: /* isb */
/* We need to break the TB after this insn