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Thu, 02 Jun 2016 13:07:20 -0700 (PDT) Received: from a0999b0126e1.ant.amazon.com ([94.230.86.227]) by smtp.gmail.com with ESMTPSA id i4sm2127090wjj.49.2016.06.02.13.07.19 (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 02 Jun 2016 13:07:20 -0700 (PDT) From: Michael Rolnik X-Google-Original-From: Michael Rolnik To: qemu-devel@nongnu.org Date: Thu, 2 Jun 2016 23:06:58 +0300 Message-Id: <1464898022-97990-6-git-send-email-rolnik@amazon.com> X-Mailer: git-send-email 2.4.9 (Apple Git-60) In-Reply-To: <1464898022-97990-1-git-send-email-rolnik@amazon.com> References: <1464898022-97990-1-git-send-email-rolnik@amazon.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [PATCH 06/10] target-avr: adding helpers for IN, OUT, SLEEP, WBR & unsupported instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Rolnik , Michael Rolnik Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Michael Rolnik --- target-avr/helper.c | 103 ++++++++++++++++++++++++++++++++++++++++++++++++++++ target-avr/helper.h | 5 +++ 2 files changed, 108 insertions(+) diff --git a/target-avr/helper.c b/target-avr/helper.c index ed22b37..450f598 100644 --- a/target-avr/helper.c +++ b/target-avr/helper.c @@ -155,6 +155,23 @@ void tlb_fill( tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, prot, mmu_idx, page_size); } +void helper_sleep( + CPUAVRState *env) +{ + CPUState *cs = CPU(avr_env_get_cpu(env)); + + cs->exception_index = EXCP_HLT; + cpu_loop_exit(cs); +} +void helper_unsupported( + CPUAVRState *env) +{ + CPUState *cs = CPU(avr_env_get_cpu(env)); + + cs->exception_index = EXCP_DEBUG; + cpu_dump_state(cs, stderr, fprintf, 0); + cpu_loop_exit(cs); +} void helper_debug( CPUAVRState *env) @@ -165,3 +182,89 @@ void helper_debug( cpu_loop_exit(cs); } +void helper_wdr( + CPUAVRState *env) +{ + CPUState *cs = CPU(avr_env_get_cpu(env)); + + cs->exception_index = EXCP_DEBUG; + cpu_loop_exit(cs); +} + +target_ulong helper_inb( + CPUAVRState *env, + uint32_t port) +{ + printf("in: io[%02x]\n", port); + + switch (port) { + case 0x3b: { + return env->rampZ; /* RAMPZ */ + } + case 0x3d: { /* SPL */ + return env->sp & 0x00ff; + } + case 0x3e: { /* SPH */ + return env->sp >> 8; + } + case 0x3f: { /* SREG */ + uint8_t sreg; + sreg = (env->sregC & 0x01) << 0 + | (env->sregZ & 0x01) << 1 + | (env->sregN & 0x01) << 2 + | (env->sregV & 0x01) << 3 + | (env->sregS & 0x01) << 4 + | (env->sregH & 0x01) << 5 + | (env->sregT & 0x01) << 6 + | (env->sregI & 0x01) << 7; + return sreg; + } + } + return 0; +} + +void helper_outb( + CPUAVRState *env, + uint32_t port, + uint32_t data) +{ + printf("out:%02x -> io[%02x]\n", data, port); + + data &= 0x000000ff; + + switch (port) { + case 0x04: { + qemu_irq irq; + CPUState *cpu = CPU(avr_env_get_cpu(env)); + irq = qdev_get_gpio_in(DEVICE(cpu), 3); + qemu_set_irq(irq, 1); + break; + } + case 0x3b: { + env->rampZ = data & 0x01; /* RAMPZ */ + break; + } + case 0x3d: { /* SPL */ + if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) { + env->sp = (env->sp & 0xff00) | (data); + } + break; + } + case 0x3e: { /* SPH */ + env->sp = (env->sp & 0x00ff) | (data << 8); + break; + } + case 0x3f: { /* SREG */ + env->sregC = (data >> 0) & 0x01; + env->sregZ = (data >> 1) & 0x01; + env->sregN = (data >> 2) & 0x01; + env->sregV = (data >> 3) & 0x01; + env->sregS = (data >> 4) & 0x01; + env->sregH = (data >> 5) & 0x01; + env->sregT = (data >> 6) & 0x01; + env->sregI = (data >> 7) & 0x01; + break; + } + } +} + diff --git a/target-avr/helper.h b/target-avr/helper.h index 017e076..5a08cfd 100644 --- a/target-avr/helper.h +++ b/target-avr/helper.h @@ -18,4 +18,9 @@ * */ +DEF_HELPER_1(wdr, void, env) DEF_HELPER_1(debug, void, env) +DEF_HELPER_1(sleep, void, env) +DEF_HELPER_1(unsupported, void, env) +DEF_HELPER_3(outb, void, env, i32, i32) +DEF_HELPER_2(inb, tl, env, i32)