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Thu, 02 Jun 2016 17:41:14 -0700 (PDT) Received: from a0999b0126e1.ant.amazon.com ([94.230.86.227]) by smtp.gmail.com with ESMTPSA id i190sm42677210wmf.10.2016.06.02.17.41.13 (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 02 Jun 2016 17:41:13 -0700 (PDT) From: Michael Rolnik X-Google-Original-From: Michael Rolnik To: qemu-devel@nongnu.org Date: Fri, 3 Jun 2016 03:40:16 +0300 Message-Id: <1464914420-17875-6-git-send-email-rolnik@amazon.com> X-Mailer: git-send-email 2.4.9 (Apple Git-60) In-Reply-To: <1464914420-17875-1-git-send-email-rolnik@amazon.com> References: <1464914420-17875-1-git-send-email-rolnik@amazon.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [PATCH 5/9] target-avr: adding AVR interrupt handling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Rolnik , Michael Rolnik Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Michael Rolnik --- target-avr/helper.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 63 insertions(+), 1 deletion(-) diff --git a/target-avr/helper.c b/target-avr/helper.c index fbab91d..bb47a87 100644 --- a/target-avr/helper.c +++ b/target-avr/helper.c @@ -31,11 +31,73 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - return false; + CPUClass *cc = CPU_GET_CLASS(cs); + AVRCPU *cpu = AVR_CPU(cs); + CPUAVRState *env = &cpu->env; + + bool ret = false; + + if (interrupt_request & CPU_INTERRUPT_RESET) { + if (cpu_interrupts_enabled(env)) { + cs->exception_index = EXCP_RESET; + cc->do_interrupt(cs); + + cs->interrupt_request &= ~CPU_INTERRUPT_RESET; + + ret = true; + } + } + if (interrupt_request & CPU_INTERRUPT_HARD) { + if (cpu_interrupts_enabled(env) && env->intsrc != 0) { + int index = __builtin_ffs(env->intsrc) - 1; + cs->exception_index = EXCP_INT(index); + cc->do_interrupt(cs); + + env->intsrc &= env->intsrc - 1; /* clear the interrupt */ + cs->interrupt_request &= ~CPU_INTERRUPT_HARD; + + ret = true; + } + } + return ret; } void avr_cpu_do_interrupt(CPUState *cs) { + AVRCPU *cpu = AVR_CPU(cs); + CPUAVRState *env = &cpu->env; + + uint32_t ret = env->pc; + int vector; + int size = avr_feature(env, AVR_FEATURE_JMP_CALL) ? 2 : 1; + int base = 0; /* TODO: where to get it */ + + if (cs->exception_index == EXCP_RESET) { + vector = 0; + } else if (env->intsrc != 0) { + vector = __builtin_ffs(env->intsrc); + } + + if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) { + stb_phys(cs->as, env->sp--, (ret & 0x0000ff)); + stb_phys(cs->as, env->sp--, (ret & 0x00ff00) >> 8); + stb_phys(cs->as, env->sp--, (ret & 0xff0000) >> 16); + + env->pc = base + vector * size; + } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) { + stb_phys(cs->as, env->sp--, (ret & 0x0000ff)); + stb_phys(cs->as, env->sp--, (ret & 0x00ff00) >> 8); + + env->pc = base + vector * size; + } else { + stb_phys(cs->as, env->sp--, (ret & 0x0000ff)); + + env->pc = base + vector * size; + } + + env->sregI = 0; /* clear Global Interrupt Flag */ + + cs->exception_index = -1; } int avr_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uint8_t *buf, int len, bool is_write)