From patchwork Mon Jun 6 14:47:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 9158607 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 13DC960759 for ; Mon, 6 Jun 2016 15:30:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 042142656B for ; Mon, 6 Jun 2016 15:30:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id ED01B28210; Mon, 6 Jun 2016 15:30:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0C2802656B for ; Mon, 6 Jun 2016 15:30:52 +0000 (UTC) Received: from localhost ([::1]:43155 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b9wUN-00042T-4T for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jun 2016 11:30:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37900) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b9vou-00006r-0o for qemu-devel@nongnu.org; Mon, 06 Jun 2016 10:48:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b9vor-0000Uz-Lb for qemu-devel@nongnu.org; Mon, 06 Jun 2016 10:47:58 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:57504) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b9vor-0000QW-Ar for qemu-devel@nongnu.org; Mon, 06 Jun 2016 10:47:57 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1b9voi-0008C4-0E for qemu-devel@nongnu.org; Mon, 06 Jun 2016 15:47:48 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 6 Jun 2016 15:47:21 +0100 Message-Id: <1465224465-21998-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1465224465-21998-1-git-send-email-peter.maydell@linaro.org> References: <1465224465-21998-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 04/28] target-arm: Don't try to set ESR IL bit in arm_cpu_do_interrupt_aarch64() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Remove some incorrect code from arm_cpu_do_interrupt_aarch64() which attempts to set the IL bit in the syndrome register based on the value of env->thumb. This is wrong in several ways: * IL doesn't indicate Thumb-vs-ARM, it indicates instruction length (which may be 16 or 32 for Thumb and is always 32 for ARM) * not every syndrome format uses IL like this -- for some IL is always set, and for some it is always clear * the code is changing esr_el[new_el] even for interrupt entry, which is not supposed to modify ESR_ELx at all Delete the code, and instead rely on the syndrome value in env->exception.syndrome having already been set up with the correct value of IL. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Message-id: 1463487258-27468-3-git-send-email-peter.maydell@linaro.org --- target-arm/helper.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 9a6ff2e..86a094d 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -6365,9 +6365,6 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) env->elr_el[new_el] = env->pc; } else { env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env); - if (!env->thumb) { - env->cp15.esr_el[new_el] |= 1 << 25; - } env->elr_el[new_el] = env->regs[15]; aarch64_sync_32_to_64(env);