From patchwork Tue Jun 7 01:37:14 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 9159695 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AFC0260759 for ; Tue, 7 Jun 2016 01:42:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9EDAE264F4 for ; Tue, 7 Jun 2016 01:42:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 922422833E; Tue, 7 Jun 2016 01:42:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 049EA264F4 for ; Tue, 7 Jun 2016 01:42:55 +0000 (UTC) Received: from localhost ([::1]:46387 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bA62g-0003AK-7U for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jun 2016 21:42:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56821) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bA62I-00038i-1y for qemu-devel@nongnu.org; Mon, 06 Jun 2016 21:42:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bA62D-0006DG-3J for qemu-devel@nongnu.org; Mon, 06 Jun 2016 21:42:30 -0400 Received: from gate.crashing.org ([63.228.1.57]:51812) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bA62C-0006DB-F7; Mon, 06 Jun 2016 21:42:25 -0400 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id u571bEtx010298; Mon, 6 Jun 2016 20:37:15 -0500 Message-ID: <1465263434.23889.11.camel@kernel.crashing.org> From: Benjamin Herrenschmidt To: qemu-ppc@nongnu.org Date: Tue, 07 Jun 2016 11:37:14 +1000 X-Mailer: Evolution 3.18.5.2 (3.18.5.2-1.fc23) Mime-Version: 1.0 X-MIME-Autoconverted: from 8bit to base64 by gate.crashing.org id u571bEtx010298 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x X-Received-From: 63.228.1.57 Subject: [Qemu-devel] [PATCH 5/6] ppc: Add missing slbfee. instruction on ppc64 BookS processors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?ISO-8859-1?Q?C=E9dric?= Le Goater , qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Used to lookup SLB entries by address, for some reason it was missing. Signed-off-by: Benjamin Herrenschmidt --- A version of this was in my earlier powernv series but had a bug, this one should be correct.  target-ppc/helper.h     |  1 +  target-ppc/mmu-hash64.c | 30 ++++++++++++++++++++++++++++++  target-ppc/translate.c  | 26 ++++++++++++++++++++++++++  3 files changed, 57 insertions(+) diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 0526322..f4410a8 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -550,6 +550,7 @@ DEF_HELPER_FLAGS_2(tlbiva, TCG_CALL_NO_RWG, void, env, tl)  DEF_HELPER_FLAGS_3(store_slb, TCG_CALL_NO_RWG, void, env, tl, tl)  DEF_HELPER_2(load_slb_esid, tl, env, tl)  DEF_HELPER_2(load_slb_vsid, tl, env, tl) +DEF_HELPER_2(find_slb_vsid, tl, env, tl)  DEF_HELPER_FLAGS_1(slbia, TCG_CALL_NO_RWG, void, env)  DEF_HELPER_FLAGS_2(slbie, TCG_CALL_NO_RWG, void, env, tl)  #endif diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index ea6e99a..668da5e 100644 --- a/target-ppc/mmu-hash64.c +++ b/target-ppc/mmu-hash64.c @@ -219,6 +219,24 @@ static int ppc_load_slb_vsid(PowerPCCPU *cpu, target_ulong rb,      return 0;  }   +static int ppc_find_slb_vsid(PowerPCCPU *cpu, target_ulong rb, +                             target_ulong *rt) +{ +    CPUPPCState *env = &cpu->env; +    ppc_slb_t *slb; + +    if (!msr_is_64bit(env, env->msr)) { +        rb &= 0xffffffff; +    } +    slb = slb_lookup(cpu, rb); +    if (slb == NULL) { +        *rt = (target_ulong)-1ul; +    } else { +        *rt = slb->vsid; +    } +    return 0; +} +  void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)  {      PowerPCCPU *cpu = ppc_env_get_cpu(env); @@ -241,6 +259,18 @@ target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)      return rt;  }   +target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb) +{ +    PowerPCCPU *cpu = ppc_env_get_cpu(env); +    target_ulong rt = 0; + +    if (ppc_find_slb_vsid(cpu, rb, &rt) < 0) { +        helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM, +                                   POWERPC_EXCP_INVAL); +    } +    return rt; +} +  target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)  {      PowerPCCPU *cpu = ppc_env_get_cpu(env); diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 33a9223..a3de142 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -4847,6 +4847,31 @@ static void gen_slbmfev(DisasContext *ctx)                               cpu_gpr[rB(ctx->opcode)]);  #endif  } + +static void gen_slbfee_(DisasContext *ctx) +{ +#if defined(CONFIG_USER_ONLY) +    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); +#else +    TCGLabel *l1, *l2; + +    if (unlikely(ctx->pr)) { +        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); +        return; +    } +    gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, +                             cpu_gpr[rB(ctx->opcode)]); +    l1 = gen_new_label(); +    l2 = gen_new_label(); +    tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); +    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); +    tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); +    tcg_gen_br(l2); +    gen_set_label(l1); +    tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); +    gen_set_label(l2); +#endif +}  #endif /* defined(TARGET_PPC64) */    /***                      Lookaside buffer management                      ***/ @@ -9972,6 +9997,7 @@ GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,  GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),  GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),  GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), +GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),  #endif  GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),  /* XXX Those instructions will need to be handled differently for