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Wed, 08 Jun 2016 03:00:47 -0700 (PDT) Received: from debian.flybox.orange ([154.123.50.93]) by smtp.googlemail.com with ESMTPSA id g129sm33441250wme.1.2016.06.08.03.00.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 08 Jun 2016 03:00:47 -0700 (PDT) From: David Kiarie To: qemu-devel@nongnu.org Date: Wed, 8 Jun 2016 13:00:32 +0300 Message-Id: <1465380032-12807-2-git-send-email-davidkiarie4@gmail.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1465380032-12807-1-git-send-email-davidkiarie4@gmail.com> References: <1465380032-12807-1-git-send-email-davidkiarie4@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [RFC] hw/i386: Composite Bus and PCI device X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ehabkost@redhat.com, mst@redhat.com, rkrcmar@redhat.com, peterx@redhat.com, alex.williamson@redhat.com, jan.kiszka@web.de, wexu@redhat.com, pbonzini@redhat.com, marcel@redhat.com, imammedo@redhat.com, davidkiarie4@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Sample composite SysBus and PCI device similar to AMD IOMMU setup Signed-off-by: David Kiarie --- hw/i386/compositedevice.c | 113 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 113 insertions(+) create mode 100644 hw/i386/compositedevice.c diff --git a/hw/i386/compositedevice.c b/hw/i386/compositedevice.c new file mode 100644 index 0000000..349e98d --- /dev/null +++ b/hw/i386/compositedevice.c @@ -0,0 +1,113 @@ +#include "qemu/osdep.h" +#include "hw/pci/pci.h" +#include "hw/i386/x86-iommu.h" +#include "hw/pci/msi.h" +#include "hw/pci/pci_bus.h" +#include "hw/sysbus.h" +#include "qom/object.h" +#include "hw/i386/pc.h" + +#define AMDVI_MMIO_SIZE 0x4000 +#define AMDVI_CAPAB_SIZE 0x18 +#define AMDVI_CAPAB_REG_SIZE 0x04 +#define AMDVI_CAPAB_ID_SEC 0xff + +#define TYPE_AMD_IOMMU_DEVICE "amd-iommu" +#define AMD_IOMMU_DEVICE(obj)\ + OBJECT_CHECK(AMDVIState, (obj), TYPE_AMD_IOMMU_DEVICE) + +#define TYPE_AMD_IOMMU_PCI "AMDVI-PCI" +#define AMD_IOMMU_PCI(obj)\ + OBJECT_CHECK(AMDVIPCIState, (obj), TYPE_AMD_IOMMU_PCI) + +typedef struct AMDVIPCIState { + PCIDevice dev; + /* PCI specific properties */ + uint8_t *capab; /* capabilities registers */ + uint32_t capab_offset; /* capability offset pointer */ +} AMDVIPCIState; + +typedef struct AMDVIState { + X86IOMMUState iommu; /* IOMMU bus device */ + AMDVIPCIState *dev; /* IOMMU PCI device */ + + uint8_t mmior[AMDVI_MMIO_SIZE]; /* read/write MMIO */ + uint8_t w1cmask[AMDVI_MMIO_SIZE]; /* read/write 1 clear mask */ + uint8_t romask[AMDVI_MMIO_SIZE]; /* MMIO read/only mask */ +} AMDVIState; + +static void amdvi_init(AMDVIState *s) +{ + /* reset PCI device */ + pci_config_set_vendor_id(s->dev->dev.config, PCI_VENDOR_ID_AMD); + pci_config_set_prog_interface(s->dev->dev.config, 00); + pci_config_set_class(s->dev->dev.config, 0x0806); +} + +static void amdvi_reset(DeviceState *dev) +{ + AMDVIState *s = AMD_IOMMU_DEVICE(dev); + + amdvi_init(s); +} + +static void amdvi_realize(DeviceState *dev, Error **errp) +{ + AMDVIState *s = AMD_IOMMU_DEVICE(dev); + PCIBus *bus = PC_MACHINE(qdev_get_machine())->bus; + + /* This device should take care of IOMMU PCI properties */ + PCIDevice *createddev = pci_create_simple(bus, -1, TYPE_AMD_IOMMU_PCI); + AMDVIPCIState *amdpcidevice = container_of(createddev, AMDVIPCIState, dev); + s->dev = amdpcidevice; +} + +static void amdvi_class_init(ObjectClass *klass, void* data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + X86IOMMUClass *dc_class = X86_IOMMU_CLASS(klass); + + dc->reset = amdvi_reset; + + dc_class->realize = amdvi_realize; +} + +static const TypeInfo amdvi = { + .name = TYPE_AMD_IOMMU_DEVICE, + .parent = TYPE_X86_IOMMU_DEVICE, + .instance_size = sizeof(AMDVIState), + .class_init = amdvi_class_init +}; + +static void amdviPCI_realize(PCIDevice *dev, Error **errp) +{ + AMDVIPCIState *s = container_of(dev, AMDVIPCIState, dev); + + /* we need to report certain PCI capabilities */ + s->capab_offset = pci_add_capability(&s->dev, AMDVI_CAPAB_ID_SEC, 0, + AMDVI_CAPAB_SIZE); + pci_add_capability(&s->dev, PCI_CAP_ID_MSI, 0, AMDVI_CAPAB_REG_SIZE); + pci_add_capability(&s->dev, PCI_CAP_ID_HT, 0, AMDVI_CAPAB_REG_SIZE); +} + +static void amdviPCI_class_init(ObjectClass *klass, void* data) +{ + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + + k->realize = amdviPCI_realize; +} + +static const TypeInfo amdviPCI = { + .name = TYPE_AMD_IOMMU_PCI, + .parent = TYPE_PCI_DEVICE, + .instance_size = sizeof(AMDVIPCIState), + .class_init = amdviPCI_class_init +}; + +static void amdviPCI_register_types(void) +{ + type_register_static(&amdviPCI); + type_register_static(&amdvi); +} + +type_init(amdviPCI_register_types);