From patchwork Thu Jun 9 16:58:13 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= X-Patchwork-Id: 9167627 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 851BC60467 for ; Thu, 9 Jun 2016 17:56:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7D34C27248 for ; Thu, 9 Jun 2016 17:56:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 70E6F28355; Thu, 9 Jun 2016 17:56:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.9 required=2.0 tests=BAYES_00,FSL_HELO_HOME, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A536D27248 for ; Thu, 9 Jun 2016 17:55:43 +0000 (UTC) Received: from localhost ([::1]:36152 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bB4B6-0005aH-S1 for patchwork-qemu-devel@patchwork.kernel.org; Thu, 09 Jun 2016 13:55:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53535) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bB3IS-0005jl-IA for qemu-devel@nongnu.org; Thu, 09 Jun 2016 12:59:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bB3IQ-00051j-0D for qemu-devel@nongnu.org; Thu, 09 Jun 2016 12:59:07 -0400 Received: from mx1.redhat.com ([209.132.183.28]:54569) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bB3IP-00051e-OV for qemu-devel@nongnu.org; Thu, 09 Jun 2016 12:59:05 -0400 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 43AD625CCE; Thu, 9 Jun 2016 16:59:05 +0000 (UTC) Received: from t530wlan.home.berrange.com.com (vpn1-5-191.ams2.redhat.com [10.36.5.191]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u59Gwbil021940; Thu, 9 Jun 2016 12:59:03 -0400 From: "Daniel P. Berrange" To: qemu-devel@nongnu.org Date: Thu, 9 Jun 2016 17:58:13 +0100 Message-Id: <1465491514-7365-20-git-send-email-berrange@redhat.com> In-Reply-To: <1465491514-7365-1-git-send-email-berrange@redhat.com> References: <1465491514-7365-1-git-send-email-berrange@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.24 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Thu, 09 Jun 2016 16:59:05 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v1 19/40] trace: split out trace events for hw/timer/ directory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Stefan Hajnoczi Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Move all trace-events for files in the hw/timer/ directory to their own file. Signed-off-by: Daniel P. Berrange --- Makefile.objs | 1 + hw/timer/trace-events | 76 +++++++++++++++++++++++++++++++++++++++++++++++++++ trace-events | 50 --------------------------------- 3 files changed, 77 insertions(+), 50 deletions(-) create mode 100644 hw/timer/trace-events diff --git a/Makefile.objs b/Makefile.objs index 5025512..fbd8454 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -136,3 +136,4 @@ trace-events-y += hw/scsi/trace-events trace-events-y += hw/nvram/trace-events trace-events-y += hw/display/trace-events trace-events-y += hw/input/trace-events +trace-events-y += hw/timer/trace-events diff --git a/hw/timer/trace-events b/hw/timer/trace-events new file mode 100644 index 0000000..d25796a --- /dev/null +++ b/hw/timer/trace-events @@ -0,0 +1,76 @@ +# Trace events for debugging and performance instrumentation +# +# This file is processed by the tracetool script during the build. +# +# To add a new trace event: +# +# 1. Choose a name for the trace event. Declare its arguments and format +# string. +# +# 2. Call the trace event from code using trace_##name, e.g. multiwrite_cb() -> +# trace_multiwrite_cb(). The source file must #include "trace.h". +# +# Format of a trace event: +# +# [disable] ( [, ] ...) "" +# +# Example: g_malloc(size_t size) "size %zu" +# +# The "disable" keyword will build without the trace event. +# +# The must be a valid as a C function name. +# +# Types should be standard C types. Use void * for pointers because the trace +# system may not have the necessary headers included. +# +# The should be a sprintf()-compatible format string. + +# hw/timer/slavio_timer.c +slavio_timer_get_out(uint64_t limit, uint32_t counthigh, uint32_t count) "limit %"PRIx64" count %x%08x" +slavio_timer_irq(uint32_t counthigh, uint32_t count) "callback: count %x%08x" +slavio_timer_mem_readl_invalid(uint64_t addr) "invalid read address %"PRIx64 +slavio_timer_mem_readl(uint64_t addr, uint32_t ret) "read %"PRIx64" = %08x" +slavio_timer_mem_writel(uint64_t addr, uint32_t val) "write %"PRIx64" = %08x" +slavio_timer_mem_writel_limit(unsigned int timer_index, uint64_t count) "processor %d user timer set to %016"PRIx64 +slavio_timer_mem_writel_counter_invalid(void) "not user timer" +slavio_timer_mem_writel_status_start(unsigned int timer_index) "processor %d user timer started" +slavio_timer_mem_writel_status_stop(unsigned int timer_index) "processor %d user timer stopped" +slavio_timer_mem_writel_mode_user(unsigned int timer_index) "processor %d changed from counter to user timer" +slavio_timer_mem_writel_mode_counter(unsigned int timer_index) "processor %d changed from user timer to counter" +slavio_timer_mem_writel_mode_invalid(void) "not system timer" +slavio_timer_mem_writel_invalid(uint64_t addr) "invalid write address %"PRIx64 + +# hw/timer/grlib_gptimer.c +grlib_gptimer_enable(int id, uint32_t count) "timer:%d set count 0x%x and run" +grlib_gptimer_disabled(int id, uint32_t config) "timer:%d Timer disable config 0x%x" +grlib_gptimer_restart(int id, uint32_t reload) "timer:%d reload val: 0x%x" +grlib_gptimer_set_scaler(uint32_t scaler, uint32_t freq) "scaler:0x%x freq: 0x%x" +grlib_gptimer_hit(int id) "timer:%d HIT" +grlib_gptimer_readl(int id, uint64_t addr, uint32_t val) "timer:%d addr 0x%"PRIx64" 0x%x" +grlib_gptimer_writel(int id, uint64_t addr, uint32_t val) "timer:%d addr 0x%"PRIx64" 0x%x" + +# hw/timer/lm32_timer.c +lm32_timer_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" +lm32_timer_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" +lm32_timer_hit(void) "timer hit" +lm32_timer_irq_state(int level) "irq state %d" + +# hw/timer/milkymist-sysctl.c +milkymist_sysctl_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x" +milkymist_sysctl_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x" +milkymist_sysctl_icap_write(uint32_t value) "value %08x" +milkymist_sysctl_start_timer0(void) "Start timer0" +milkymist_sysctl_stop_timer0(void) "Stop timer0" +milkymist_sysctl_start_timer1(void) "Start timer1" +milkymist_sysctl_stop_timer1(void) "Stop timer1" +milkymist_sysctl_pulse_irq_timer0(void) "Pulse IRQ Timer0" +milkymist_sysctl_pulse_irq_timer1(void) "Pulse IRQ Timer1" + +# hw/timer/aspeed_timer.c +aspeed_timer_ctrl_enable(uint8_t i, bool enable) "Timer %" PRIu8 ": %d" +aspeed_timer_ctrl_external_clock(uint8_t i, bool enable) "Timer %" PRIu8 ": %d" +aspeed_timer_ctrl_overflow_interrupt(uint8_t i, bool enable) "Timer %" PRIu8 ": %d" +aspeed_timer_ctrl_pulse_enable(uint8_t i, bool enable) "Timer %" PRIu8 ": %d" +aspeed_timer_set_ctrl2(uint32_t value) "Value: 0x%" PRIx32 +aspeed_timer_set_value(int timer, int reg, uint32_t value) "Timer %d register %d: 0x%" PRIx32 +aspeed_timer_read(uint64_t offset, unsigned size, uint64_t value) "From 0x%" PRIx64 ": of size %u: 0x%" PRIx64 diff --git a/trace-events b/trace-events index 33ee352..1bde21b 100644 --- a/trace-events +++ b/trace-events @@ -42,21 +42,6 @@ virtio_balloon_get_config(uint32_t num_pages, uint32_t actual) "num_pages: %d ac virtio_balloon_set_config(uint32_t actual, uint32_t oldactual) "actual: %d oldactual: %d" virtio_balloon_to_target(uint64_t target, uint32_t num_pages) "balloon target: %"PRIx64" num_pages: %d" -# hw/timer/slavio_timer.c -slavio_timer_get_out(uint64_t limit, uint32_t counthigh, uint32_t count) "limit %"PRIx64" count %x%08x" -slavio_timer_irq(uint32_t counthigh, uint32_t count) "callback: count %x%08x" -slavio_timer_mem_readl_invalid(uint64_t addr) "invalid read address %"PRIx64 -slavio_timer_mem_readl(uint64_t addr, uint32_t ret) "read %"PRIx64" = %08x" -slavio_timer_mem_writel(uint64_t addr, uint32_t val) "write %"PRIx64" = %08x" -slavio_timer_mem_writel_limit(unsigned int timer_index, uint64_t count) "processor %d user timer set to %016"PRIx64 -slavio_timer_mem_writel_counter_invalid(void) "not user timer" -slavio_timer_mem_writel_status_start(unsigned int timer_index) "processor %d user timer started" -slavio_timer_mem_writel_status_stop(unsigned int timer_index) "processor %d user timer stopped" -slavio_timer_mem_writel_mode_user(unsigned int timer_index) "processor %d changed from counter to user timer" -slavio_timer_mem_writel_mode_counter(unsigned int timer_index) "processor %d changed from user timer to counter" -slavio_timer_mem_writel_mode_invalid(void) "not system timer" -slavio_timer_mem_writel_invalid(uint64_t addr) "invalid write address %"PRIx64 - # hw/dma/rc4030.c jazzio_read(uint64_t addr, uint32_t ret) "read reg[0x%"PRIx64"] = 0x%x" jazzio_write(uint64_t addr, uint32_t val) "write reg[0x%"PRIx64"] = 0x%x" @@ -99,15 +84,6 @@ system_wakeup_request(int reason) "reason=%d" qemu_system_shutdown_request(void) "" qemu_system_powerdown_request(void) "" -# hw/timer/grlib_gptimer.c -grlib_gptimer_enable(int id, uint32_t count) "timer:%d set count 0x%x and run" -grlib_gptimer_disabled(int id, uint32_t config) "timer:%d Timer disable config 0x%x" -grlib_gptimer_restart(int id, uint32_t reload) "timer:%d reload val: 0x%x" -grlib_gptimer_set_scaler(uint32_t scaler, uint32_t freq) "scaler:0x%x freq: 0x%x" -grlib_gptimer_hit(int id) "timer:%d HIT" -grlib_gptimer_readl(int id, uint64_t addr, uint32_t val) "timer:%d addr 0x%"PRIx64" 0x%x" -grlib_gptimer_writel(int id, uint64_t addr, uint32_t val) "timer:%d addr 0x%"PRIx64" 0x%x" - # hw/sparc/leon3.c leon3_set_irq(int intno) "Set CPU IRQ %d" leon3_reset_irq(int intno) "Reset CPU IRQ %d" @@ -119,27 +95,10 @@ spice_vmc_register_interface(void *scd) "spice vmc registered interface %p" spice_vmc_unregister_interface(void *scd) "spice vmc unregistered interface %p" spice_vmc_event(int event) "spice vmc event %d" -# hw/timer/lm32_timer.c -lm32_timer_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" -lm32_timer_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" -lm32_timer_hit(void) "timer hit" -lm32_timer_irq_state(int level) "irq state %d" - # hw/sd/milkymist-memcard.c milkymist_memcard_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x" milkymist_memcard_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x" -# hw/timer/milkymist-sysctl.c -milkymist_sysctl_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x" -milkymist_sysctl_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x" -milkymist_sysctl_icap_write(uint32_t value) "value %08x" -milkymist_sysctl_start_timer0(void) "Start timer0" -milkymist_sysctl_stop_timer0(void) "Stop timer0" -milkymist_sysctl_start_timer1(void) "Start timer1" -milkymist_sysctl_stop_timer1(void) "Stop timer1" -milkymist_sysctl_pulse_irq_timer0(void) "Pulse IRQ Timer0" -milkymist_sysctl_pulse_irq_timer1(void) "Pulse IRQ Timer1" - # hw/isa/pc87312.c pc87312_io_read(uint32_t addr, uint32_t val) "read addr=%x val=%x" pc87312_io_write(uint32_t addr, uint32_t val) "write addr=%x val=%x" @@ -617,12 +576,3 @@ user_handle_signal(void *env, int target_sig) "env=%p signal %d" user_host_signal(void *env, int host_sig, int target_sig) "env=%p signal %d (target %d(" user_queue_signal(void *env, int target_sig) "env=%p signal %d" user_s390x_restore_sigregs(void *env, uint64_t sc_psw_addr, uint64_t env_psw_addr) "env=%p frame psw.addr %"PRIx64 " current psw.addr %"PRIx64 - -# hw/timer/aspeed_timer.c -aspeed_timer_ctrl_enable(uint8_t i, bool enable) "Timer %" PRIu8 ": %d" -aspeed_timer_ctrl_external_clock(uint8_t i, bool enable) "Timer %" PRIu8 ": %d" -aspeed_timer_ctrl_overflow_interrupt(uint8_t i, bool enable) "Timer %" PRIu8 ": %d" -aspeed_timer_ctrl_pulse_enable(uint8_t i, bool enable) "Timer %" PRIu8 ": %d" -aspeed_timer_set_ctrl2(uint32_t value) "Value: 0x%" PRIx32 -aspeed_timer_set_value(int timer, int reg, uint32_t value) "Timer %d register %d: 0x%" PRIx32 -aspeed_timer_read(uint64_t offset, unsigned size, uint64_t value) "From 0x%" PRIx64 ": of size %u: 0x%" PRIx64