From patchwork Thu Jun 9 16:58:14 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= X-Patchwork-Id: 9167555 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1670F607DA for ; Thu, 9 Jun 2016 17:31:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 068D026490 for ; Thu, 9 Jun 2016 17:31:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EFA77282F9; Thu, 9 Jun 2016 17:31:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.9 required=2.0 tests=BAYES_00,FSL_HELO_HOME, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 554E826490 for ; Thu, 9 Jun 2016 17:31:44 +0000 (UTC) Received: from localhost ([::1]:36028 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bB3nz-0000ae-EA for patchwork-qemu-devel@patchwork.kernel.org; Thu, 09 Jun 2016 13:31:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53554) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bB3IU-0005mq-Jw for qemu-devel@nongnu.org; Thu, 09 Jun 2016 12:59:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bB3IS-000522-6J for qemu-devel@nongnu.org; Thu, 09 Jun 2016 12:59:09 -0400 Received: from mx1.redhat.com ([209.132.183.28]:44607) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bB3IR-00051v-UK for qemu-devel@nongnu.org; Thu, 09 Jun 2016 12:59:08 -0400 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 6D8851F576; Thu, 9 Jun 2016 16:59:07 +0000 (UTC) Received: from t530wlan.home.berrange.com.com (vpn1-5-191.ams2.redhat.com [10.36.5.191]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u59Gwbim021940; Thu, 9 Jun 2016 12:59:05 -0400 From: "Daniel P. Berrange" To: qemu-devel@nongnu.org Date: Thu, 9 Jun 2016 17:58:14 +0100 Message-Id: <1465491514-7365-21-git-send-email-berrange@redhat.com> In-Reply-To: <1465491514-7365-1-git-send-email-berrange@redhat.com> References: <1465491514-7365-1-git-send-email-berrange@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.24 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Thu, 09 Jun 2016 16:59:07 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v1 20/40] trace: split out trace events for hw/dma/ directory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Stefan Hajnoczi Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Move all trace-events for files in the hw/dma/ directory to their own file. Signed-off-by: Daniel P. Berrange --- Makefile.objs | 1 + hw/dma/trace-events | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++++ trace-events | 31 ----------------------------- 3 files changed, 58 insertions(+), 31 deletions(-) create mode 100644 hw/dma/trace-events diff --git a/Makefile.objs b/Makefile.objs index fbd8454..b05f290 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -137,3 +137,4 @@ trace-events-y += hw/nvram/trace-events trace-events-y += hw/display/trace-events trace-events-y += hw/input/trace-events trace-events-y += hw/timer/trace-events +trace-events-y += hw/dma/trace-events diff --git a/hw/dma/trace-events b/hw/dma/trace-events new file mode 100644 index 0000000..ff73c9f --- /dev/null +++ b/hw/dma/trace-events @@ -0,0 +1,57 @@ +# Trace events for debugging and performance instrumentation +# +# This file is processed by the tracetool script during the build. +# +# To add a new trace event: +# +# 1. Choose a name for the trace event. Declare its arguments and format +# string. +# +# 2. Call the trace event from code using trace_##name, e.g. multiwrite_cb() -> +# trace_multiwrite_cb(). The source file must #include "trace.h". +# +# Format of a trace event: +# +# [disable] ( [, ] ...) "" +# +# Example: g_malloc(size_t size) "size %zu" +# +# The "disable" keyword will build without the trace event. +# +# The must be a valid as a C function name. +# +# Types should be standard C types. Use void * for pointers because the trace +# system may not have the necessary headers included. +# +# The should be a sprintf()-compatible format string. + +# hw/dma/rc4030.c +jazzio_read(uint64_t addr, uint32_t ret) "read reg[0x%"PRIx64"] = 0x%x" +jazzio_write(uint64_t addr, uint32_t val) "write reg[0x%"PRIx64"] = 0x%x" +rc4030_read(uint64_t addr, uint32_t ret) "read reg[0x%"PRIx64"] = 0x%x" +rc4030_write(uint64_t addr, uint32_t val) "write reg[0x%"PRIx64"] = 0x%x" + +# hw/dma/sparc32_dma.c +ledma_memory_read(uint64_t addr) "DMA read addr 0x%"PRIx64 +ledma_memory_write(uint64_t addr) "DMA write addr 0x%"PRIx64 +sparc32_dma_set_irq_raise(void) "Raise IRQ" +sparc32_dma_set_irq_lower(void) "Lower IRQ" +espdma_memory_read(uint32_t addr) "DMA read addr 0x%08x" +espdma_memory_write(uint32_t addr) "DMA write addr 0x%08x" +sparc32_dma_mem_readl(uint64_t addr, uint32_t ret) "read dmareg %"PRIx64": 0x%08x" +sparc32_dma_mem_writel(uint64_t addr, uint32_t old, uint32_t val) "write dmareg %"PRIx64": 0x%08x -> 0x%08x" +sparc32_dma_enable_raise(void) "Raise DMA enable" +sparc32_dma_enable_lower(void) "Lower DMA enable" + +# hw/dma/sun4m_iommu.c +sun4m_iommu_mem_readl(uint64_t addr, uint32_t ret) "read reg[%"PRIx64"] = %x" +sun4m_iommu_mem_writel(uint64_t addr, uint32_t val) "write reg[%"PRIx64"] = %x" +sun4m_iommu_mem_writel_ctrl(uint64_t iostart) "iostart = %"PRIx64 +sun4m_iommu_mem_writel_tlbflush(uint32_t val) "tlb flush %x" +sun4m_iommu_mem_writel_pgflush(uint32_t val) "page flush %x" +sun4m_iommu_page_get_flags(uint64_t pa, uint64_t iopte, uint32_t ret) "get flags addr %"PRIx64" => pte %"PRIx64", *pte = %x" +sun4m_iommu_translate_pa(uint64_t addr, uint64_t pa, uint32_t iopte) "xlate dva %"PRIx64" => pa %"PRIx64" iopte = %x" +sun4m_iommu_bad_addr(uint64_t addr) "bad addr %"PRIx64 + +# hw/dma/i8257.c +i8257_unregistered_dma(int nchan, int dma_pos, int dma_len) "unregistered DMA channel used nchan=%d dma_pos=%d dma_len=%d" diff --git a/trace-events b/trace-events index 1bde21b..a47fc4b 100644 --- a/trace-events +++ b/trace-events @@ -42,40 +42,12 @@ virtio_balloon_get_config(uint32_t num_pages, uint32_t actual) "num_pages: %d ac virtio_balloon_set_config(uint32_t actual, uint32_t oldactual) "actual: %d oldactual: %d" virtio_balloon_to_target(uint64_t target, uint32_t num_pages) "balloon target: %"PRIx64" num_pages: %d" -# hw/dma/rc4030.c -jazzio_read(uint64_t addr, uint32_t ret) "read reg[0x%"PRIx64"] = 0x%x" -jazzio_write(uint64_t addr, uint32_t val) "write reg[0x%"PRIx64"] = 0x%x" -rc4030_read(uint64_t addr, uint32_t ret) "read reg[0x%"PRIx64"] = 0x%x" -rc4030_write(uint64_t addr, uint32_t val) "write reg[0x%"PRIx64"] = 0x%x" - -# hw/dma/sparc32_dma.c -ledma_memory_read(uint64_t addr) "DMA read addr 0x%"PRIx64 -ledma_memory_write(uint64_t addr) "DMA write addr 0x%"PRIx64 -sparc32_dma_set_irq_raise(void) "Raise IRQ" -sparc32_dma_set_irq_lower(void) "Lower IRQ" -espdma_memory_read(uint32_t addr) "DMA read addr 0x%08x" -espdma_memory_write(uint32_t addr) "DMA write addr 0x%08x" -sparc32_dma_mem_readl(uint64_t addr, uint32_t ret) "read dmareg %"PRIx64": 0x%08x" -sparc32_dma_mem_writel(uint64_t addr, uint32_t old, uint32_t val) "write dmareg %"PRIx64": 0x%08x -> 0x%08x" -sparc32_dma_enable_raise(void) "Raise DMA enable" -sparc32_dma_enable_lower(void) "Lower DMA enable" - # hw/sparc/sun4m.c sun4m_cpu_interrupt(unsigned int level) "Set CPU IRQ %d" sun4m_cpu_reset_interrupt(unsigned int level) "Reset CPU IRQ %d" sun4m_cpu_set_irq_raise(int level) "Raise CPU IRQ %d" sun4m_cpu_set_irq_lower(int level) "Lower CPU IRQ %d" -# hw/dma/sun4m_iommu.c -sun4m_iommu_mem_readl(uint64_t addr, uint32_t ret) "read reg[%"PRIx64"] = %x" -sun4m_iommu_mem_writel(uint64_t addr, uint32_t val) "write reg[%"PRIx64"] = %x" -sun4m_iommu_mem_writel_ctrl(uint64_t iostart) "iostart = %"PRIx64 -sun4m_iommu_mem_writel_tlbflush(uint32_t val) "tlb flush %x" -sun4m_iommu_mem_writel_pgflush(uint32_t val) "page flush %x" -sun4m_iommu_page_get_flags(uint64_t pa, uint64_t iopte, uint32_t ret) "get flags addr %"PRIx64" => pte %"PRIx64", *pte = %x" -sun4m_iommu_translate_pa(uint64_t addr, uint64_t pa, uint32_t iopte) "xlate dva %"PRIx64" => pa %"PRIx64" iopte = %x" -sun4m_iommu_bad_addr(uint64_t addr) "bad addr %"PRIx64 - # vl.c vm_state_notify(int running, int reason) "running %d reason %d" load_file(const char *name, const char *path) "name %s location %s" @@ -533,9 +505,6 @@ kvm_clear_cmma(int rc) "CMMA: clearing with result code %d" kvm_failed_cpu_state_set(int cpu_index, uint8_t state, const char *msg) "Warning: Unable to set cpu %d state %" PRIu8 " to KVM: %s" kvm_sigp_finished(uint8_t order, int cpu_index, int dst_index, int cc) "SIGP: Finished order %u on cpu %d -> cpu %d with cc=%d" -# hw/dma/i8257.c -i8257_unregistered_dma(int nchan, int dma_pos, int dma_len) "unregistered DMA channel used nchan=%d dma_pos=%d dma_len=%d" - # target-s390x/cpu.c cpu_set_state(int cpu_index, uint8_t state) "setting cpu %d state to %" PRIu8 cpu_halt(int cpu_index) "halting cpu %d"