From patchwork Mon Jun 13 23:58:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 9174753 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 122C16044F for ; Tue, 14 Jun 2016 00:20:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0415627D45 for ; Tue, 14 Jun 2016 00:20:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EBB0528047; Tue, 14 Jun 2016 00:20:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DAD9527D45 for ; Tue, 14 Jun 2016 00:20:42 +0000 (UTC) Received: from localhost ([::1]:60104 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bCc5y-00058s-1w for patchwork-qemu-devel@patchwork.kernel.org; Mon, 13 Jun 2016 20:20:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38723) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bCbl7-0002H5-EA for qemu-devel@nongnu.org; Mon, 13 Jun 2016 19:59:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bCbl4-0004Ss-I5 for qemu-devel@nongnu.org; Mon, 13 Jun 2016 19:59:08 -0400 Received: from mail-qt0-x243.google.com ([2607:f8b0:400d:c0d::243]:34087) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bCbl4-0004Sm-DT for qemu-devel@nongnu.org; Mon, 13 Jun 2016 19:59:06 -0400 Received: by mail-qt0-x243.google.com with SMTP id 9so5840971qtg.1 for ; Mon, 13 Jun 2016 16:59:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=OUHK1XM7enmX93qEhgndlumtITeOHWfwfi2OT5nZj60=; b=PU/3MUGo8TqXopk7saRUlCBJXaje7mINwn2dX5KNYleuexdqCrmCOlyr/C9YCGMvwa Sica8C1BkmtKzU1JtFPcJymteOnac08JkVzDT3lbBUkhBA2P9c/g4fMlQBUI8ja0QMyC HuP8mxceQE+/fdSuXBb4pw92bmgNXc0kk9eEFXMbvujom3/OBKSfC3QFAWSST0LizmOB NKHZPtpzB0T0B905Qls0oSvoTdmA2WqH3ps4NxZsyCDcQh99rT27jDsFNzeM51gqRVux n9go4TDzYYhkiiVD0HpesiXhIS0lAHHkaokZSb9imIK7o+LIFp0Z3hoJ/WpPbscxq9il QtEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=OUHK1XM7enmX93qEhgndlumtITeOHWfwfi2OT5nZj60=; b=Ck3RsUQ7TknhQsBM3V/Zj6IuwRLeARd3aKUxHpxbVBiSN9VCfqnSKV2iBNEjgQQNhY lwviZnHJ938m9Ke63xmygK/6fpAOHwiv7rbRdZzrfCCANDK3/ml+18qZ3FTxc3RfWlww iJBR+8s/ZysNw/l/eHQ4Yv1C+MUXOcdd8gHHmP22VoqiORHmnPFU/ePyIVPEpJNaA3gB FTMSwr10R4SumnbiotHU8xJE4uvJCOHNBywNWuCebrIAt+oeajBeDg21Kbh5Y27S2Y2i uu5LE/lOGyWWpcezz8UfJmi82RmV/4DVKBO7wLiDggskOXbTmRf4+A6r9h8HhiODYNdT pPsA== X-Gm-Message-State: ALyK8tL5NNsT7wrHPPNndtoFEWW8Sqnuhem8Xdi9E6AvTZiSmd66zvD4sxey5e+wW45low== X-Received: by 10.237.41.134 with SMTP id o6mr5831300qtd.12.1465862345775; Mon, 13 Jun 2016 16:59:05 -0700 (PDT) Received: from bigtime.com (71-37-54-227.tukw.qwest.net. [71.37.54.227]) by smtp.gmail.com with ESMTPSA id q200sm7547234qke.31.2016.06.13.16.59.05 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 Jun 2016 16:59:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 13 Jun 2016 16:58:11 -0700 Message-Id: <1465862305-14090-12-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1465862305-14090-1-git-send-email-rth@twiddle.net> References: <1465862305-14090-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400d:c0d::243 Subject: [Qemu-devel] [PATCH 11/25] target-openrisc: Rationalize immediate extraction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The architecture manual is consistent in using "I" for signed fields and "K" for unsigned fields. Mirror that. Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target-openrisc/translate.c | 200 +++++++++++++++++--------------------------- 1 file changed, 75 insertions(+), 125 deletions(-) diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index 62129b8..6ca0420 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -113,23 +113,6 @@ void openrisc_translate_init(void) } } -static inline int zero_extend(unsigned int val, int width) -{ - return val & ((1 << width) - 1); -} - -static inline int sign_extend(unsigned int val, int width) -{ - int sval; - - /* LSL */ - val <<= TARGET_LONG_BITS - width; - sval = val; - /* ASR. */ - sval >>= TARGET_LONG_BITS - width; - return sval; -} - static inline void gen_sync_flags(DisasContext *dc) { /* Sync the tb dependent flag between translate and runtime. */ @@ -153,29 +136,23 @@ static void gen_illegal_exception(DisasContext *dc) dc->is_jmp = DISAS_UPDATE; } -/* not used yet, open it when we need or64. */ -/*#ifdef TARGET_OPENRISC64 -static void check_ob64s(DisasContext *dc) -{ - if (!(dc->flags & CPUCFGR_OB64S)) { - gen_illegal_exception(dc); - } -} +#define check_ob64s(dc) \ + do { \ + gen_illegal_exception(dc); \ + return; \ + } while (0) -static void check_of64s(DisasContext *dc) -{ - if (!(dc->flags & CPUCFGR_OF64S)) { - gen_illegal_exception(dc); - } -} +#define check_of64s(dc) \ + do { \ + gen_illegal_exception(dc); \ + return; \ + } while (0) -static void check_ov64s(DisasContext *dc) -{ - if (!(dc->flags & CPUCFGR_OV64S)) { - gen_illegal_exception(dc); - } -} -#endif*/ +#define check_ov64s(dc) \ + do { \ + gen_illegal_exception(dc); \ + return; \ + } while (0) static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) { @@ -205,11 +182,9 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) } } -static void gen_jump(DisasContext *dc, uint32_t imm, uint32_t reg, uint32_t op0) +static void gen_jump(DisasContext *dc, int32_t n26, uint32_t reg, uint32_t op0) { - target_ulong tmp_pc; - /* N26, 26bits imm */ - tmp_pc = sign_extend((imm<<2), 26) + dc->pc; + target_ulong tmp_pc = dc->pc + n26 * 4; switch (op0) { case 0x00: /* l.j */ @@ -584,7 +559,8 @@ static void dec_misc(DisasContext *dc, uint32_t insn) uint32_t op0, op1; uint32_t ra, rb, rd; uint32_t L6, K5; - uint32_t I16, I5, I11, N26, tmp; + uint32_t K16, K5_11; + int32_t I16, I5_11, N26; TCGMemOp mop; TCGv t0; @@ -595,11 +571,11 @@ static void dec_misc(DisasContext *dc, uint32_t insn) rd = extract32(insn, 21, 5); L6 = extract32(insn, 5, 6); K5 = extract32(insn, 0, 5); - I16 = extract32(insn, 0, 16); - I5 = extract32(insn, 21, 5); - I11 = extract32(insn, 0, 11); - N26 = extract32(insn, 0, 26); - tmp = (I5<<11) + I11; + K16 = extract32(insn, 0, 16); + I16 = (int16_t)K16; + N26 = sextract32(insn, 0, 26); + K5_11 = (extract32(insn, 21, 5) << 11) | extract32(insn, 0, 11); + I5_11 = (int16_t)K5_11; switch (op0) { case 0x00: /* l.j */ @@ -645,12 +621,10 @@ static void dec_misc(DisasContext *dc, uint32_t insn) break; case 0x13: /* l.maci */ - LOG_DIS("l.maci %d, r%d, %d\n", I5, ra, I16); - { - TCGv imm = tcg_const_tl(sign_extend(I16, 16)); - gen_mac(dc, cpu_R[ra], imm); - tcg_temp_free(imm); - } + LOG_DIS("l.maci r%d, %d\n", ra, I16); + t0 = tcg_const_tl(I16); + gen_mac(dc, cpu_R[ra], t0); + tcg_temp_free(t0); break; case 0x09: /* l.rfe */ @@ -701,52 +675,40 @@ static void dec_misc(DisasContext *dc, uint32_t insn) LOG_DIS("l.cust8\n"); break; -/* not used yet, open it when we need or64. */ -/*#ifdef TARGET_OPENRISC64 - case 0x20: l.ld + case 0x20: /* l.ld */ LOG_DIS("l.ld r%d, r%d, %d\n", rd, ra, I16); check_ob64s(dc); mop = MO_TEQ; goto do_load; -#endif*/ - case 0x21: /* l.lwz */ LOG_DIS("l.lwz r%d, r%d, %d\n", rd, ra, I16); mop = MO_TEUL; goto do_load; - case 0x22: /* l.lws */ LOG_DIS("l.lws r%d, r%d, %d\n", rd, ra, I16); mop = MO_TESL; goto do_load; - case 0x23: /* l.lbz */ LOG_DIS("l.lbz r%d, r%d, %d\n", rd, ra, I16); mop = MO_UB; goto do_load; - case 0x24: /* l.lbs */ LOG_DIS("l.lbs r%d, r%d, %d\n", rd, ra, I16); mop = MO_SB; goto do_load; - case 0x25: /* l.lhz */ LOG_DIS("l.lhz r%d, r%d, %d\n", rd, ra, I16); mop = MO_TEUW; goto do_load; - case 0x26: /* l.lhs */ LOG_DIS("l.lhs r%d, r%d, %d\n", rd, ra, I16); mop = MO_TESW; goto do_load; - do_load: - { - TCGv t0 = tcg_temp_new(); - tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16)); - tcg_gen_qemu_ld_tl(cpu_R[rd], t0, dc->mem_idx, mop); - tcg_temp_free(t0); - } + t0 = tcg_temp_new(); + tcg_gen_addi_tl(t0, cpu_R[ra], I16); + tcg_gen_qemu_ld_tl(cpu_R[rd], t0, dc->mem_idx, mop); + tcg_temp_free(t0); break; case 0x27: /* l.addi */ @@ -764,18 +726,18 @@ static void dec_misc(DisasContext *dc, uint32_t insn) break; case 0x29: /* l.andi */ - LOG_DIS("l.andi r%d, r%d, %d\n", rd, ra, I16); - tcg_gen_andi_tl(cpu_R[rd], cpu_R[ra], zero_extend(I16, 16)); + LOG_DIS("l.andi r%d, r%d, %d\n", rd, ra, K16); + tcg_gen_andi_tl(cpu_R[rd], cpu_R[ra], K16); break; case 0x2a: /* l.ori */ - LOG_DIS("l.ori r%d, r%d, %d\n", rd, ra, I16); - tcg_gen_ori_tl(cpu_R[rd], cpu_R[ra], zero_extend(I16, 16)); + LOG_DIS("l.ori r%d, r%d, %d\n", rd, ra, K16); + tcg_gen_ori_tl(cpu_R[rd], cpu_R[ra], K16); break; case 0x2b: /* l.xori */ LOG_DIS("l.xori r%d, r%d, %d\n", rd, ra, I16); - tcg_gen_xori_tl(cpu_R[rd], cpu_R[ra], sign_extend(I16, 16)); + tcg_gen_xori_tl(cpu_R[rd], cpu_R[ra], I16); break; case 0x2c: /* l.muli */ @@ -786,70 +748,57 @@ static void dec_misc(DisasContext *dc, uint32_t insn) break; case 0x2d: /* l.mfspr */ - LOG_DIS("l.mfspr r%d, r%d, %d\n", rd, ra, I16); - { + LOG_DIS("l.mfspr r%d, r%d, %d\n", rd, ra, K16); #if defined(CONFIG_USER_ONLY) - return; + return; #else - TCGv_i32 ti = tcg_const_i32(I16); - if (dc->mem_idx == MMU_USER_IDX) { - gen_illegal_exception(dc); - return; - } - gen_helper_mfspr(cpu_R[rd], cpu_env, cpu_R[rd], cpu_R[ra], ti); - tcg_temp_free_i32(ti); -#endif + if (dc->mem_idx == MMU_USER_IDX) { + gen_illegal_exception(dc); + return; } + t0 = tcg_const_i32(K16); + gen_helper_mfspr(cpu_R[rd], cpu_env, cpu_R[rd], cpu_R[ra], t0); + tcg_temp_free(t0); +#endif break; case 0x30: /* l.mtspr */ - LOG_DIS("l.mtspr %d, r%d, r%d, %d\n", I5, ra, rb, I11); - { + LOG_DIS("l.mtspr r%d, r%d, %d\n", ra, rb, K5_11); #if defined(CONFIG_USER_ONLY) - return; + return; #else - TCGv_i32 im = tcg_const_i32(tmp); - if (dc->mem_idx == MMU_USER_IDX) { - gen_illegal_exception(dc); - return; - } - gen_helper_mtspr(cpu_env, cpu_R[ra], cpu_R[rb], im); - tcg_temp_free_i32(im); -#endif + if (dc->mem_idx == MMU_USER_IDX) { + gen_illegal_exception(dc); + return; } + t0 = tcg_const_tl(K5_11); + gen_helper_mtspr(cpu_env, cpu_R[ra], cpu_R[rb], t0); + tcg_temp_free(t0); +#endif break; -/* not used yet, open it when we need or64. */ -/*#ifdef TARGET_OPENRISC64 - case 0x34: l.sd - LOG_DIS("l.sd %d, r%d, r%d, %d\n", I5, ra, rb, I11); + case 0x34: /* l.sd */ + LOG_DIS("l.sd r%d, r%d, %d\n", ra, rb, I5_11); check_ob64s(dc); mop = MO_TEQ; goto do_store; -#endif*/ - case 0x35: /* l.sw */ - LOG_DIS("l.sw %d, r%d, r%d, %d\n", I5, ra, rb, I11); + LOG_DIS("l.sw r%d, r%d, %d\n", ra, rb, I5_11); mop = MO_TEUL; goto do_store; - case 0x36: /* l.sb */ - LOG_DIS("l.sb %d, r%d, r%d, %d\n", I5, ra, rb, I11); + LOG_DIS("l.sb r%d, r%d, %d\n", ra, rb, I5_11); mop = MO_UB; goto do_store; - case 0x37: /* l.sh */ - LOG_DIS("l.sh %d, r%d, r%d, %d\n", I5, ra, rb, I11); + LOG_DIS("l.sh r%d, r%d, %d\n", ra, rb, I5_11); mop = MO_TEUW; goto do_store; - do_store: - { - TCGv t0 = tcg_temp_new(); - tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16)); - tcg_gen_qemu_st_tl(cpu_R[rb], t0, dc->mem_idx, mop); - tcg_temp_free(t0); - } + t0 = tcg_temp_new(); + tcg_gen_addi_tl(t0, cpu_R[ra], I5_11); + tcg_gen_qemu_st_tl(cpu_R[rb], t0, dc->mem_idx, mop); + tcg_temp_free(t0); break; default: @@ -886,30 +835,32 @@ static void dec_mac(DisasContext *dc, uint32_t insn) static void dec_logic(DisasContext *dc, uint32_t insn) { uint32_t op0; - uint32_t rd, ra, L6; + uint32_t rd, ra, L6, S6; op0 = extract32(insn, 6, 2); rd = extract32(insn, 21, 5); ra = extract32(insn, 16, 5); L6 = extract32(insn, 0, 6); + S6 = L6 & (TARGET_LONG_BITS - 1); switch (op0) { case 0x00: /* l.slli */ LOG_DIS("l.slli r%d, r%d, %d\n", rd, ra, L6); - tcg_gen_shli_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f)); + tcg_gen_shli_tl(cpu_R[rd], cpu_R[ra], S6); break; case 0x01: /* l.srli */ LOG_DIS("l.srli r%d, r%d, %d\n", rd, ra, L6); - tcg_gen_shri_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f)); + tcg_gen_shri_tl(cpu_R[rd], cpu_R[ra], S6); break; case 0x02: /* l.srai */ LOG_DIS("l.srai r%d, r%d, %d\n", rd, ra, L6); - tcg_gen_sari_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f)); break; + tcg_gen_sari_tl(cpu_R[rd], cpu_R[ra], S6); + break; case 0x03: /* l.rori */ LOG_DIS("l.rori r%d, r%d, %d\n", rd, ra, L6); - tcg_gen_rotri_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f)); + tcg_gen_rotri_tl(cpu_R[rd], cpu_R[ra], S6); break; default: @@ -1018,13 +969,12 @@ static void dec_comp(DisasContext *dc, uint32_t insn) static void dec_compi(DisasContext *dc, uint32_t insn) { uint32_t op0; - uint32_t ra, I16; + uint32_t ra; + int32_t I16; op0 = extract32(insn, 21, 5); ra = extract32(insn, 16, 5); - I16 = extract32(insn, 0, 16); - - I16 = sign_extend(I16, 16); + I16 = sextract32(insn, 0, 16); switch (op0) { case 0x0: /* l.sfeqi */