From patchwork Mon Jun 13 23:58:17 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 9174757 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A00176044F for ; Tue, 14 Jun 2016 00:23:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 91F0427D45 for ; Tue, 14 Jun 2016 00:23:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8629C28047; Tue, 14 Jun 2016 00:23:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B934627D45 for ; Tue, 14 Jun 2016 00:23:33 +0000 (UTC) Received: from localhost ([::1]:60114 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bCc8i-0007QK-U0 for patchwork-qemu-devel@patchwork.kernel.org; Mon, 13 Jun 2016 20:23:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38768) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bCblA-0002LW-Kd for qemu-devel@nongnu.org; Mon, 13 Jun 2016 19:59:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bCbl9-0004UN-BX for qemu-devel@nongnu.org; Mon, 13 Jun 2016 19:59:12 -0400 Received: from mail-qt0-x243.google.com ([2607:f8b0:400d:c0d::243]:33553) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bCbl9-0004UH-5N for qemu-devel@nongnu.org; Mon, 13 Jun 2016 19:59:11 -0400 Received: by mail-qt0-x243.google.com with SMTP id 72so5850302qtb.0 for ; Mon, 13 Jun 2016 16:59:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=q4hvYAD3oKVERFqlm5qEwG0qmgwxwWvx87alQfy5dGk=; b=Ve/7x4RqLmF7Gt04IX/78Cgpm6nnnZQpJ86QfGQO0NDBhPHAtyxfcB1cIep8KXy0Gy 6FwUFZh8ywSucY1fuRmkWHxo5AtfAKjZD1biJ5+B5spcbAieswuRpOmJbmHDJeKJlmHY pYD331A9jYOGGxo7jSoXhlPpXULA9e9xP8XWbpyMUcTu1jfXS+MCQI0z77V7HUQDHMRI Ep239chDr14M38QhjwmXjR914dUFzjaQCWGljuohkVNYCb8WisDrpgQPjQ4DLxjqhHOS T42gnEDT31NRw8mlw70LKzX4JAGz/TGrvpmfUS01U/1SylQpMjDvKVKOPnGtro+BJDRA u6Wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=q4hvYAD3oKVERFqlm5qEwG0qmgwxwWvx87alQfy5dGk=; b=gI8MeIgkE3XRCPVuExp2e1VMGUHVImmD7TpxFLFihJsTIKxVcTA/g0tz1o/YaZhzko /lE/jaETuV//uHVTG3UEJklumixXW6UNtWgPISWw66O00HW7TBTp9wB18/Ttsv3ZXzSV j+Kbqb3Lm/XIQXOcc6KNR4Z4D1I8j2l4SP3PmpTIGsIFtYieBNre2KfyZWUUfVIzkZkY 0V04nC/Y4Flz8kNbomdYuUkeTWdP2Pg/kA6uc/6c8HGHcPLIXcui0zrgd5OvTwI8aO/s TwP64rGb9gxxG/Vm6HgOlWgtswa2ljdr/imq0yU3KkgClNDsAK5gOy/ZtltQelVK8fx6 W0xQ== X-Gm-Message-State: ALyK8tIKz+/78zrAV1nTfsg3Q83wpxMLQvCYSogT0D2QbWQ90lCfS7k6AfqRcvxQKAkQ9w== X-Received: by 10.200.45.89 with SMTP id o25mr16199700qta.22.1465862350573; Mon, 13 Jun 2016 16:59:10 -0700 (PDT) Received: from bigtime.com (71-37-54-227.tukw.qwest.net. [71.37.54.227]) by smtp.gmail.com with ESMTPSA id q200sm7547234qke.31.2016.06.13.16.59.09 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 Jun 2016 16:59:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 13 Jun 2016 16:58:17 -0700 Message-Id: <1465862305-14090-18-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1465862305-14090-1-git-send-email-rth@twiddle.net> References: <1465862305-14090-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400d:c0d::243 Subject: [Qemu-devel] [PATCH 17/25] target-openrisc: Implement lwa, swa X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Richard Henderson --- linux-user/main.c | 45 ++++++++++++++++++++++++ target-openrisc/cpu.c | 1 + target-openrisc/cpu.h | 9 +++++ target-openrisc/interrupt.c | 1 + target-openrisc/interrupt_helper.c | 1 + target-openrisc/mmu.c | 1 + target-openrisc/translate.c | 70 ++++++++++++++++++++++++++++++++++++++ 7 files changed, 128 insertions(+) diff --git a/linux-user/main.c b/linux-user/main.c index f8a8764..51af5d1 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -2720,6 +2720,48 @@ error: #endif #ifdef TARGET_OPENRISC +static void do_store_exclusive(CPUOpenRISCState *env) +{ + target_ulong addr, val, tmp; + target_siginfo_t info; + int ret = 0; + + addr = env->lock_addr; + tmp = env->lock_st_addr; + env->lock_addr = -1; + env->lock_st_addr = 0; + + start_exclusive(); + mmap_lock(); + + if (addr == tmp) { + if (get_user_u32(val, addr)) { + goto do_sigsegv; + } + if (val == env->lock_value) { + if (put_user_u32(env->lock_st_value, addr)) { + goto do_sigsegv; + } + ret = 1; + } + } + env->sr_f = ret; + env->pc += 4; + + mmap_unlock(); + end_exclusive(); + return; + + do_sigsegv: + mmap_unlock(); + end_exclusive(); + + info.si_signo = TARGET_SIGSEGV; + info.si_errno = 0; + info.si_code = TARGET_SEGV_MAPERR; + info._sifields._sigfault._addr = addr; + queue_signal(env, TARGET_SIGSEGV, &info); +} void cpu_loop(CPUOpenRISCState *env) { @@ -2795,6 +2837,9 @@ void cpu_loop(CPUOpenRISCState *env) case EXCP_NR: qemu_log_mask(CPU_LOG_INT, "\nNR\n"); break; + case EXCP_SWA: + do_store_exclusive(env); + break; default: EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n", trapnr); diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index 155913f..e6f6186 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -55,6 +55,7 @@ static void openrisc_cpu_reset(CPUState *s) cpu->env.pc = 0x100; cpu->env.sr = SR_FO | SR_SM; + cpu->env.lock_addr = -1; s->exception_index = -1; cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP; diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index 8c130da..bb9540f 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -169,6 +169,8 @@ enum { EXCP_FPE = 0xd, EXCP_TRAP = 0xe, EXCP_NR, + /* For usermode emulation. */ + EXCP_SWA, }; /* Supervisor register */ @@ -295,6 +297,13 @@ typedef struct CPUOpenRISCState { uint32_t fpcsr; /* Float register */ float_status fp_status; + target_ulong lock_addr; + target_ulong lock_value; +#ifdef CONFIG_USER_ONLY + target_ulong lock_st_addr; + target_ulong lock_st_value; +#endif + uint32_t flags; /* cpu_flags, we only use it for exception in solt so far. */ diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c index 36ca131..77c2d00 100644 --- a/target-openrisc/interrupt.c +++ b/target-openrisc/interrupt.c @@ -55,6 +55,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->sr &= ~SR_TEE; env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; + env->lock_addr = -1; if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) { env->pc = (cs->exception_index << 8); diff --git a/target-openrisc/interrupt_helper.c b/target-openrisc/interrupt_helper.c index 71e14ce..68d1598 100644 --- a/target-openrisc/interrupt_helper.c +++ b/target-openrisc/interrupt_helper.c @@ -34,6 +34,7 @@ void HELPER(rfe)(CPUOpenRISCState *env) cpu->env.pc = cpu->env.epcr; cpu->env.npc = cpu->env.epcr; cpu_set_sr(&cpu->env, cpu->env.esr); + cpu->env.lock_addr = -1; #ifndef CONFIG_USER_ONLY if (cpu->env.sr & SR_DME) { diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c index 505dcdc..56b11d3 100644 --- a/target-openrisc/mmu.c +++ b/target-openrisc/mmu.c @@ -174,6 +174,7 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu, cs->exception_index = exception; cpu->env.eear = address; + cpu->env.lock_addr = -1; } #ifndef CONFIG_USER_ONLY diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index e539693..0ad0c39 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -58,6 +58,8 @@ static TCGv cpu_ppc; static TCGv cpu_sr_f; /* bf/bnf, F flag taken */ static TCGv cpu_sr_cy; /* carry (unsigned overflow) */ static TCGv cpu_sr_ov; /* signed overflow */ +static TCGv cpu_lock_addr; +static TCGv cpu_lock_value; static TCGv_i32 fpcsr; static TCGv_i64 cpu_mac; /* MACHI:MACLO */ static TCGv_i32 env_flags; @@ -93,6 +95,12 @@ void openrisc_translate_init(void) offsetof(CPUOpenRISCState, sr_cy), "sr_cy"); cpu_sr_ov = tcg_global_mem_new(cpu_env, offsetof(CPUOpenRISCState, sr_ov), "sr_ov"); + cpu_lock_addr = tcg_global_mem_new(cpu_env, + offsetof(CPUOpenRISCState, lock_addr), + "lock_addr"); + cpu_lock_value = tcg_global_mem_new(cpu_env, + offsetof(CPUOpenRISCState, lock_value), + "lock_value"); fpcsr = tcg_global_mem_new_i32(cpu_env, offsetof(CPUOpenRISCState, fpcsr), "fpcsr"); @@ -478,6 +486,58 @@ static void gen_msbu(DisasContext *dc, TCGv srca, TCGv srcb) gen_ove_cy(dc); } +static void gen_lwa(DisasContext *dc, TCGv rd, TCGv ra, int32_t ofs) +{ + TCGv ea = tcg_temp_new(); + + tcg_gen_addi_tl(ea, ra, ofs); + tcg_gen_qemu_ld_tl(rd, ea, dc->mem_idx, MO_TEUL); + tcg_gen_mov_tl(cpu_lock_addr, ea); + tcg_gen_mov_tl(cpu_lock_value, rd); + tcg_temp_free(ea); +} + +static void gen_swa(DisasContext *dc, TCGv rb, TCGv ra, int32_t ofs) +{ +#ifdef CONFIG_USER_ONLY + TCGv ea = tcg_temp_new(); + tcg_gen_addi_tl(ea, ra, ofs); + tcg_gen_st_tl(ea, cpu_env, offsetof(CPUOpenRISCState, lock_st_addr)); + tcg_temp_free(ea); + + tcg_gen_st32_tl(rb, cpu_env, offsetof(CPUOpenRISCState, lock_st_value)); + + tcg_gen_movi_tl(cpu_pc, dc->pc); + gen_exception(dc, EXCP_SWA); + dc->is_jmp = DISAS_UPDATE; +#else + TCGv ea, val; + TCGLabel *lab_fail, *lab_done; + + ea = tcg_temp_new(); + tcg_gen_addi_tl(ea, ra, ofs); + + lab_fail = gen_new_label(); + lab_done = gen_new_label(); + tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_lock_addr, lab_fail); + tcg_temp_free(ea); + + val = tcg_temp_new(); + tcg_gen_qemu_ld_tl(val, cpu_lock_addr, dc->mem_idx, MO_TEUL); + tcg_gen_brcond_tl(TCG_COND_NE, val, cpu_lock_value, lab_fail); + + tcg_gen_qemu_st_tl(rb, cpu_lock_addr, dc->mem_idx, MO_TEUL); + tcg_gen_movi_tl(cpu_sr_f, 1); + tcg_gen_br(lab_done); + + gen_set_label(lab_fail); + tcg_gen_movi_tl(cpu_sr_f, 0); + + gen_set_label(lab_done); + tcg_gen_movi_tl(cpu_lock_addr, -1); +#endif +} + static void dec_calc(DisasContext *dc, uint32_t insn) { uint32_t op0, op1, op2; @@ -732,6 +792,11 @@ static void dec_misc(DisasContext *dc, uint32_t insn) } break; + case 0x1b: /* l.lwa */ + LOG_DIS("l.lwa r%d, r%d, %d\n", rd, ra, I16); + gen_lwa(dc, cpu_R[rd], cpu_R[ra], I16); + break; + case 0x1c: /* l.cust1 */ LOG_DIS("l.cust1\n"); break; @@ -858,6 +923,11 @@ static void dec_misc(DisasContext *dc, uint32_t insn) } break; + case 0x33: /* l.swa */ + LOG_DIS("l.swa r%d, r%d, %d\n", ra, rb, I5_11); + gen_swa(dc, cpu_R[rb], cpu_R[ra], I5_11); + break; + case 0x34: /* l.sd */ LOG_DIS("l.sd r%d, r%d, %d\n", ra, rb, I5_11); check_ob64s(dc);