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[71.37.54.227]) by smtp.gmail.com with ESMTPSA id q200sm7547234qke.31.2016.06.13.16.59.01 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 Jun 2016 16:59:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 13 Jun 2016 16:58:06 -0700 Message-Id: <1465862305-14090-7-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1465862305-14090-1-git-send-email-rth@twiddle.net> References: <1465862305-14090-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400d:c0d::243 Subject: [Qemu-devel] [PATCH 06/25] target-openrisc: Put SR[OVE] in TB flags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Removes a call at execution time for overflow exceptions. Signed-off-by: Richard Henderson --- target-openrisc/cpu.h | 4 ++-- target-openrisc/exception_helper.c | 2 +- target-openrisc/translate.c | 24 +++++++++++++++--------- 3 files changed, 18 insertions(+), 12 deletions(-) diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index 1ea7607..af63f58 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -396,8 +396,8 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, { *pc = env->pc; *cs_base = 0; - /* D_FLAG -- branch instruction exception */ - *flags = (env->flags & D_FLAG); + /* D_FLAG -- branch instruction exception, OVE overflow trap enable. */ + *flags = (env->flags & D_FLAG) | (env->sr & SR_OVE); } static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) diff --git a/target-openrisc/exception_helper.c b/target-openrisc/exception_helper.c index 561384a..6ae795f 100644 --- a/target-openrisc/exception_helper.c +++ b/target-openrisc/exception_helper.c @@ -31,7 +31,7 @@ void HELPER(exception)(CPUOpenRISCState *env, uint32_t excp) void HELPER(ove)(CPUOpenRISCState *env, target_ulong test) { - if (unlikely(test) && (env->sr & SR_OVE)) { + if (unlikely(test)) { OpenRISCCPU *cpu = openrisc_env_get_cpu(env); CPUState *cs = CPU(cpu); diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index 48bd5f7..1cb726a 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -130,8 +130,8 @@ static inline int sign_extend(unsigned int val, int width) static inline void gen_sync_flags(DisasContext *dc) { /* Sync the tb dependent flag between translate and runtime. */ - if (dc->tb_flags != dc->synced_flags) { - tcg_gen_movi_tl(env_flags, dc->tb_flags); + if ((dc->tb_flags ^ dc->synced_flags) & D_FLAG) { + tcg_gen_movi_tl(env_flags, dc->tb_flags & D_FLAG); dc->synced_flags = dc->tb_flags; } } @@ -250,20 +250,26 @@ static void gen_jump(DisasContext *dc, uint32_t imm, uint32_t reg, uint32_t op0) static void gen_ove_cy(DisasContext *dc, TCGv cy) { - gen_helper_ove(cpu_env, cy); + if (dc->tb_flags & SR_OVE) { + gen_helper_ove(cpu_env, cy); + } } static void gen_ove_ov(DisasContext *dc, TCGv ov) { - gen_helper_ove(cpu_env, ov); + if (dc->tb_flags & SR_OVE) { + gen_helper_ove(cpu_env, ov); + } } static void gen_ove_cyov(DisasContext *dc, TCGv cy, TCGv ov) { - TCGv t0 = tcg_temp_new(); - tcg_gen_or_tl(t0, cy, ov); - gen_helper_ove(cpu_env, t0); - tcg_temp_free(t0); + if (dc->tb_flags & SR_OVE) { + TCGv t0 = tcg_temp_new(); + tcg_gen_or_tl(t0, cy, ov); + gen_helper_ove(cpu_env, t0); + tcg_temp_free(t0); + } } static void gen_add(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) @@ -1430,7 +1436,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb) dc->flags = cpu->env.cpucfgr; dc->mem_idx = cpu_mmu_index(&cpu->env, false); dc->synced_flags = dc->tb_flags = tb->flags; - dc->delayed_branch = !!(dc->tb_flags & D_FLAG); + dc->delayed_branch = (dc->tb_flags & D_FLAG) != 0; dc->singlestep_enabled = cs->singlestep_enabled; if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { qemu_log("-----------------------------------------\n");