From patchwork Tue Jun 14 14:38:19 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 9176165 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4E8396075D for ; Tue, 14 Jun 2016 15:28:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 421BC24151 for ; Tue, 14 Jun 2016 15:28:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 36F4227E78; Tue, 14 Jun 2016 15:28:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AFCD124151 for ; Tue, 14 Jun 2016 15:28:33 +0000 (UTC) Received: from localhost ([::1]:36138 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bCqGW-00012n-PA for patchwork-qemu-devel@patchwork.kernel.org; Tue, 14 Jun 2016 11:28:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57636) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bCpjZ-0001Ng-EV for qemu-devel@nongnu.org; Tue, 14 Jun 2016 10:54:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bCpjX-0002jY-8R for qemu-devel@nongnu.org; Tue, 14 Jun 2016 10:54:28 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:57761) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bCpjW-0002fK-Vh for qemu-devel@nongnu.org; Tue, 14 Jun 2016 10:54:27 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1bCpUC-0006LC-UJ; Tue, 14 Jun 2016 15:38:36 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 14 Jun 2016 15:38:19 +0100 Message-Id: <1465915112-29272-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1465915112-29272-1-git-send-email-peter.maydell@linaro.org> References: <1465915112-29272-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH v3 07/20] hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structure X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org, Shlomo Pongratz , Shlomo Pongratz , Pavel Fedin , Shannon Zhao , Christoffer Dall Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Move the GICv3 parent_irq and parent_fiq pointers into the GICv3CPUState structure rather than giving them their own array. This will make it easy to assert the IRQ and FIQ lines for a particular CPU interface without having to know or calculate the CPU index for the GICv3CPUState we are working on. Signed-off-by: Peter Maydell Reviewed-by: Shannon Zhao --- hw/intc/arm_gicv3_common.c | 7 ++----- include/hw/intc/arm_gicv3_common.h | 5 ++--- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index bf6949f..1557833 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -72,14 +72,11 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, i = s->num_irq - GIC_INTERNAL + GIC_INTERNAL * s->num_cpu; qdev_init_gpio_in(DEVICE(s), handler, i); - s->parent_irq = g_malloc(s->num_cpu * sizeof(qemu_irq)); - s->parent_fiq = g_malloc(s->num_cpu * sizeof(qemu_irq)); - for (i = 0; i < s->num_cpu; i++) { - sysbus_init_irq(sbd, &s->parent_irq[i]); + sysbus_init_irq(sbd, &s->cpu[i].parent_irq); } for (i = 0; i < s->num_cpu; i++) { - sysbus_init_irq(sbd, &s->parent_fiq[i]); + sysbus_init_irq(sbd, &s->cpu[i].parent_fiq); } memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s, diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h index bd364a7..cc6ac74 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -134,6 +134,8 @@ typedef struct GICv3CPUState GICv3CPUState; struct GICv3CPUState { GICv3State *gic; CPUState *cpu; + qemu_irq parent_irq; + qemu_irq parent_fiq; /* Redistributor */ uint32_t level; /* Current IRQ level */ @@ -168,9 +170,6 @@ struct GICv3State { SysBusDevice parent_obj; /*< public >*/ - qemu_irq *parent_irq; - qemu_irq *parent_fiq; - MemoryRegion iomem_dist; /* Distributor */ MemoryRegion iomem_redist; /* Redistributors */