From patchwork Fri Jun 17 08:14:10 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chao Peng X-Patchwork-Id: 9183033 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B6F8B60776 for ; Fri, 17 Jun 2016 08:26:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A48102838A for ; Fri, 17 Jun 2016 08:26:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 99874283A8; Fri, 17 Jun 2016 08:26:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AE01A2838A for ; Fri, 17 Jun 2016 08:26:17 +0000 (UTC) Received: from localhost ([::1]:54744 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bDp6W-0007Vu-Ff for patchwork-qemu-devel@patchwork.kernel.org; Fri, 17 Jun 2016 04:26:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44929) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bDp0v-00021P-Np for qemu-devel@nongnu.org; Fri, 17 Jun 2016 04:20:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bDp0s-0007BE-Rc for qemu-devel@nongnu.org; Fri, 17 Jun 2016 04:20:28 -0400 Received: from mga02.intel.com ([134.134.136.20]:55279) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bDp0s-0007Ag-EZ for qemu-devel@nongnu.org; Fri, 17 Jun 2016 04:20:26 -0400 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP; 17 Jun 2016 01:20:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,482,1459839600"; d="scan'208";a="989448619" Received: from vmm-docker1.bj.intel.com ([10.240.193.52]) by fmsmga001.fm.intel.com with ESMTP; 17 Jun 2016 01:20:24 -0700 From: Chao Peng To: qemu-devel@nongnu.org Date: Fri, 17 Jun 2016 04:14:10 -0400 Message-Id: <1466151257-96318-3-git-send-email-chao.p.peng@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1466151257-96318-1-git-send-email-chao.p.peng@linux.intel.com> References: <1466151257-96318-1-git-send-email-chao.p.peng@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.20 Subject: [Qemu-devel] [RFC 2/9] pci: introduce light weight PCIE Host emulation pci-lite X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Haozhong Zhang , Xiao Guangrong , Eduardo Habkost , "Michael S. Tsirkin" , Paolo Bonzini , gor Mammedov , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP A minimal emulation for PCIE host bridge that supports 0xcf8/0xcfc and MMFG. Actually there is already a gpex there, but it is designed mainly for ARM and is not quite suitable for x86: - it lacks things like PCI hole properties which are required by ACPI. - the corresponding driver in Linux is designed to work with device tree which is not suitable for x86. For this case, additional guest driver is even not needed. Currently MMFG size is limited to 1M, which means only 1 bus is supported, this is aimed to reduce the scan time in guest. And it doesn't have a valid vendor ID/device ID assigned so guest may not recognize it, the functionality however is expected to be OK. Signed-off-by: Chao Peng --- default-configs/i386-softmmu.mak | 1 + default-configs/x86_64-softmmu.mak | 1 + hw/pci-host/Makefile.objs | 1 + hw/pci-host/pci_lite.c | 259 +++++++++++++++++++++++++++++++++++++ include/hw/i386/pc.h | 5 + 5 files changed, 267 insertions(+) create mode 100644 hw/pci-host/pci_lite.c diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak index b177e52..421ad0a 100644 --- a/default-configs/i386-softmmu.mak +++ b/default-configs/i386-softmmu.mak @@ -38,6 +38,7 @@ CONFIG_PFLASH_CFI01=y CONFIG_TPM_TIS=$(CONFIG_TPM) CONFIG_MC146818RTC=y CONFIG_PAM=y +CONFIG_PCI_LITE=y CONFIG_PCI_PIIX=y CONFIG_WDT_IB700=y CONFIG_XEN_I386=$(CONFIG_XEN) diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-softmmu.mak index 6e3b312..f197cfd 100644 --- a/default-configs/x86_64-softmmu.mak +++ b/default-configs/x86_64-softmmu.mak @@ -38,6 +38,7 @@ CONFIG_PFLASH_CFI01=y CONFIG_TPM_TIS=$(CONFIG_TPM) CONFIG_MC146818RTC=y CONFIG_PAM=y +CONFIG_PCI_LITE=y CONFIG_PCI_PIIX=y CONFIG_WDT_IB700=y CONFIG_XEN_I386=$(CONFIG_XEN) diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs index 45f1f0e..5dbb034 100644 --- a/hw/pci-host/Makefile.objs +++ b/hw/pci-host/Makefile.objs @@ -16,3 +16,4 @@ common-obj-$(CONFIG_FULONG) += bonito.o common-obj-$(CONFIG_PCI_PIIX) += piix.o common-obj-$(CONFIG_PCI_Q35) += q35.o common-obj-$(CONFIG_PCI_GENERIC) += gpex.o +common-obj-$(CONFIG_PCI_LITE) += pci_lite.o diff --git a/hw/pci-host/pci_lite.c b/hw/pci-host/pci_lite.c new file mode 100644 index 0000000..15b388d --- /dev/null +++ b/hw/pci-host/pci_lite.c @@ -0,0 +1,259 @@ +/* + * QEMU Light weight PCI Host Bridge Emulation + * + * Copyright (C) 2016 Intel Corporation. + * + * Author: + * Chao Peng + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/hw.h" +#include "hw/i386/pc.h" +#include "hw/pci/pci.h" +#include "hw/pci/pcie_host.h" +#include "hw/isa/isa.h" +#include "hw/sysbus.h" +#include "qapi/error.h" +#include "qemu/range.h" +#include "hw/xen/xen.h" +#include "sysemu/sysemu.h" +#include "hw/i386/ioapic.h" +#include "qapi/visitor.h" +#include "qemu/error-report.h" + +#define TYPE_PCI_LITE_HOST "pci-lite-host" +#define TYPE_PCI_LITE_DEVICE "pci-lite-device" + +#define PCI_LITE_HOST(obj) \ + OBJECT_CHECK(PCILiteHost, (obj), TYPE_PCI_LITE_HOST) + +#define PCI_LITE_NUM_IRQS 4 +#define PCI_LITE_PCIEXBAR_BASE 0xb0000000 +#define PCI_LITE_PCIEXBAR_SIZE (0x100000) /* 1M for bus 0 */ + +typedef struct PCILiteHost { + /*< private >*/ + PCIExpressHost parent_obj; + /*< public >*/ + + PcPciInfo pci_info; + qemu_irq irq[PCI_LITE_NUM_IRQS]; + uint64_t pci_hole64_size; +} PCILiteHost; + +static void pci_lite_get_pci_hole_start(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + PCILiteHost *s = PCI_LITE_HOST(obj); + uint32_t value = s->pci_info.w32.begin; + + visit_type_uint32(v, name, &value, errp); +} + +static void pci_lite_get_pci_hole_end(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + PCILiteHost *s = PCI_LITE_HOST(obj); + uint32_t value = s->pci_info.w32.end; + + visit_type_uint32(v, name, &value, errp); +} + +static void pci_lite_get_pci_hole64_start(Object *obj, Visitor *v, + const char *name, + void *opaque, Error **errp) +{ + PCIHostState *h = PCI_HOST_BRIDGE(obj); + Range w64; + + pci_bus_get_w64_range(h->bus, &w64); + + visit_type_uint64(v, name, &w64.begin, errp); +} + +static void pci_lite_get_pci_hole64_end(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + PCIHostState *h = PCI_HOST_BRIDGE(obj); + Range w64; + + pci_bus_get_w64_range(h->bus, &w64); + + visit_type_uint64(v, name, &w64.end, errp); +} + +static void pci_lite_initfn(Object *obj) +{ + PCIHostState *s = PCI_HOST_BRIDGE(obj); + PCILiteHost *d = PCI_LITE_HOST(obj); + + memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s, + "pci-conf-idx", 4); + memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s, + "pci-conf-data", 4); + + object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int", + pci_lite_get_pci_hole_start, + NULL, NULL, NULL, NULL); + + object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int", + pci_lite_get_pci_hole_end, + NULL, NULL, NULL, NULL); + + object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int", + pci_lite_get_pci_hole64_start, + NULL, NULL, NULL, NULL); + + object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int", + pci_lite_get_pci_hole64_end, + NULL, NULL, NULL, NULL); + + d->pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS; +} + +static void pci_lite_set_irq(void *opaque, int irq_num, int level) +{ + PCILiteHost *d = opaque; + + qemu_set_irq(d->irq[irq_num], level); +} + +static void pci_lite_realize(DeviceState *dev, Error **errp) +{ + PCIHostState *s = PCI_HOST_BRIDGE(dev); + PCILiteHost *d = PCI_LITE_HOST(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + int i; + + sysbus_add_io(sbd, 0xcf8, &s->conf_mem); + sysbus_init_ioports(sbd, 0xcf8, 4); + + sysbus_add_io(sbd, 0xcfc, &s->data_mem); + sysbus_init_ioports(sbd, 0xcfc, 4); + + for (i = 0; i < PCI_LITE_NUM_IRQS; i++) { + sysbus_init_irq(sbd, &d->irq[i]); + } +} + +PCIBus *pci_lite_init(MemoryRegion *address_space_mem, + MemoryRegion *address_space_io, + MemoryRegion *pci_address_space) +{ + DeviceState *dev; + PCIHostState *pci; + PCIExpressHost *pcie; + PCILiteHost *pci_lite; + + dev = qdev_create(NULL, TYPE_PCI_LITE_HOST); + pci = PCI_HOST_BRIDGE(dev); + pcie = PCIE_HOST_BRIDGE(dev); + + pci->bus = pci_register_bus(dev, "pcie.0", pci_lite_set_irq, + pci_swizzle_map_irq_fn, pci, pci_address_space, + address_space_io, 0, 4, TYPE_PCIE_BUS); + + object_property_add_child(qdev_get_machine(), "pcilite", OBJECT(dev), NULL); + qdev_init_nofail(dev); + + pci_lite = PCI_LITE_HOST(dev); + pci_lite->pci_info.w32.begin = PCI_LITE_PCIEXBAR_BASE + + PCI_LITE_PCIEXBAR_SIZE; + + pcie_host_mmcfg_update(pcie, 1, PCI_LITE_PCIEXBAR_BASE, + PCI_LITE_PCIEXBAR_SIZE); + e820_add_entry(PCI_LITE_PCIEXBAR_BASE, PCI_LITE_PCIEXBAR_SIZE, + E820_RESERVED); + + /* setup pci memory mapping */ + pc_pci_as_mapping_init(OBJECT(dev), address_space_mem, pci_address_space); + + pci_create_simple(pci->bus, 0, TYPE_PCI_LITE_DEVICE); + return pci->bus; +} + +static const char *pci_lite_root_bus_path(PCIHostState *host_bridge, + PCIBus *rootbus) +{ + return "0000:00"; +} + +static Property pci_lite_props[] = { + DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, PCILiteHost, + parent_obj.base_addr, PCI_LITE_PCIEXBAR_BASE), + DEFINE_PROP_UINT64(PCIE_HOST_MCFG_SIZE, PCILiteHost, + parent_obj.size, PCI_LITE_PCIEXBAR_SIZE), + DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, PCILiteHost, + pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE), + DEFINE_PROP_END_OF_LIST(), +}; + +static void pci_lite_host_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); + + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); + dc->realize = pci_lite_realize; + dc->props = pci_lite_props; + hc->root_bus_path = pci_lite_root_bus_path; +} + +static const TypeInfo pci_lite_host_info = { + .name = TYPE_PCI_LITE_HOST, + .parent = TYPE_PCIE_HOST_BRIDGE, + .instance_size = sizeof(PCILiteHost), + .instance_init = pci_lite_initfn, + .class_init = pci_lite_host_class_init, +}; + +static void pci_lite_device_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + + k->class_id = PCI_CLASS_BRIDGE_HOST; + dc->desc = "Host bridge"; + /* + * PCI-facing part of the host bridge, not usable without the + * host-facing part, which can't be device_add'ed, yet. + */ + dc->cannot_instantiate_with_device_add_yet = true; + dc->hotpluggable = false; +} + +static const TypeInfo pci_lite_device_info = { + .name = TYPE_PCI_LITE_DEVICE, + .parent = TYPE_PCI_DEVICE, + .class_init = pci_lite_device_class_init, +}; + +static void pci_lite_register_types(void) +{ + type_register_static(&pci_lite_device_info); + type_register_static(&pci_lite_host_info); +} + +type_init(pci_lite_register_types) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 7c3506e..ad7533b 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -285,6 +285,11 @@ DeviceState *pm_lite_init(PCIBus *bus, int devfn, qemu_irq sci_irq); /* hpet.c */ extern int no_hpet; +/* pci_lite.c */ +PCIBus *pci_lite_init(MemoryRegion *address_space_mem, + MemoryRegion *address_space_io, + MemoryRegion *pci_memory); + /* piix_pci.c */ struct PCII440FXState; typedef struct PCII440FXState PCII440FXState;