From patchwork Fri Jun 17 13:11:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Efimov Vasily X-Patchwork-Id: 9184021 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C7AF8608A2 for ; Fri, 17 Jun 2016 13:41:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B844628380 for ; Fri, 17 Jun 2016 13:41:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id ACEBD28396; Fri, 17 Jun 2016 13:41:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 420A428380 for ; Fri, 17 Jun 2016 13:41:11 +0000 (UTC) Received: from localhost ([::1]:57589 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bDu1G-0001Zj-3P for patchwork-qemu-devel@patchwork.kernel.org; Fri, 17 Jun 2016 09:41:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58040) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bDtZ0-0004Hd-9M for qemu-devel@nongnu.org; Fri, 17 Jun 2016 09:11:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bDtYy-0000rs-5H for qemu-devel@nongnu.org; Fri, 17 Jun 2016 09:11:57 -0400 Received: from smtp.ispras.ru ([83.149.199.79]:53762) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bDtYn-0000in-N8; Fri, 17 Jun 2016 09:11:46 -0400 Received: from real.intra.ispras.ru (unknown [83.149.199.91]) by smtp.ispras.ru (Postfix) with ESMTP id EDCDC2041D; Fri, 17 Jun 2016 16:11:12 +0300 (MSK) From: Efimov Vasily To: qemu-devel@nongnu.org Date: Fri, 17 Jun 2016 16:11:01 +0300 Message-Id: <1466169069-29375-6-git-send-email-real@ispras.ru> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1466169069-29375-1-git-send-email-real@ispras.ru> References: <1466169069-29375-1-git-send-email-real@ispras.ru> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 83.149.199.79 Subject: [Qemu-devel] [PATCH 05/13] Q35: implement property interfece to several parameters X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Peter Maydell , Eduardo Habkost , qemu-block@nongnu.org, "Michael S. Tsirkin" , Efimov Vasily , Max Reitz , Gerd Hoffmann , Paolo Bonzini , Kirill Batuzov , John Snow , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP During creation of Q35 instance several parameters are set using direct access. It violates Qemu device model. Correctly, the parameters should be handled as object properties. The patch adds four link type properties for fields: mch.ram_memory mch.pci_address_space mch.system_memory mch.address_space_io And, it adds two size type properties for fields: mch.below_4g_mem_size mch.above_4g_mem_size Signed-off-by: Efimov Vasily --- hw/pci-host/q35.c | 20 ++++++++++++++++++++ include/hw/i386/pc.h | 2 ++ include/hw/pci-host/q35.h | 5 +++++ 3 files changed, 27 insertions(+) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 70f897e..ab337b8 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -127,6 +127,10 @@ static Property mch_props[] = { DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE), DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0), + DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost, + mch.below_4g_mem_size, 0), + DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost, + mch.above_4g_mem_size, 0), DEFINE_PROP_END_OF_LIST(), }; @@ -177,6 +181,22 @@ static void q35_host_initfn(Object *obj) q35_host_get_mmcfg_size, NULL, NULL, NULL, NULL); + object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, + (Object **) &s->mch.ram_memory, object_property_allow_set_link, + 0, NULL); + + object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, + (Object **) &s->mch.pci_address_space, + object_property_allow_set_link, 0, NULL); + + object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, + (Object **) &s->mch.system_memory, object_property_allow_set_link, + 0, NULL); + + object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, + (Object **) &s->mch.address_space_io, + object_property_allow_set_link, 0, NULL); + /* Leave enough space for the biggest MCFG BAR */ /* TODO: this matches current bios behaviour, but * it's not a power of two, which means an MTRR diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index aab3a53..5193ae9 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -238,6 +238,8 @@ void pc_guest_info_init(PCMachineState *pcms); #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start" #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end" #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size" +#define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size" +#define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size" #define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL) diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h index c5c073d..8b4bde3 100644 --- a/include/hw/pci-host/q35.h +++ b/include/hw/pci-host/q35.h @@ -78,6 +78,11 @@ typedef struct Q35PCIHost { * gmch part */ +#define MCH_HOST_PROP_RAM_MEM "ram-mem" +#define MCH_HOST_PROP_PCI_MEM "pci-mem" +#define MCH_HOST_PROP_SYSTEM_MEM "system-mem" +#define MCH_HOST_PROP_IO_MEM "io-mem" + /* PCI configuration */ #define MCH_HOST_BRIDGE "MCH"