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[94.39.188.118]) by smtp.gmail.com with ESMTPSA id r127sm7910146wmf.21.2016.06.20.07.39.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 20 Jun 2016 07:39:25 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Mon, 20 Jun 2016 16:39:19 +0200 Message-Id: <1466433559-30930-4-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1466433559-30930-1-git-send-email-pbonzini@redhat.com> References: <1466433559-30930-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [PATCH 3/3] ich9: unify pic and ioapic IRQ vectors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: real@ispras.ru Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP ich9->pic and ich9->ioapic differ for the first 16 GSIs (because ich9->pic is wired to 8259+IOAPIC but ich9->ioapic is wired to IOAPIC only). However, ich9->ioapic is never used for the first 16 GSIs, so the two vectors can be merged. Signed-off-by: Paolo Bonzini Reviewed-by: Efimov Vasily --- hw/i386/pc_q35.c | 3 +-- hw/isa/lpc_ich9.c | 4 ++-- include/hw/i386/ich9.h | 3 +-- 3 files changed, 4 insertions(+), 6 deletions(-) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index e4b541f..78afd4f 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -184,8 +184,7 @@ static void pc_q35_init(MachineState *machine) PC_MACHINE_ACPI_DEVICE_PROP, &error_abort); ich9_lpc = ICH9_LPC_DEVICE(lpc); - ich9_lpc->pic = gsi; - ich9_lpc->ioapic = gsi_state->ioapic_irq; + ich9_lpc->gsi = gsi; pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, ICH9_LPC_NB_PIRQS); pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 446797b..7703357 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -225,7 +225,7 @@ static void ich9_lpc_update_pic(ICH9LPCState *lpc, int gsi) pic_level |= lpc->sci_level; } - qemu_set_irq(lpc->pic[gsi], pic_level); + qemu_set_irq(lpc->gsi[gsi], pic_level); } /* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */ @@ -250,7 +250,7 @@ static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi) level |= lpc->sci_level; } - qemu_set_irq(lpc->ioapic[gsi], level); + qemu_set_irq(lpc->gsi[gsi], level); } void ich9_lpc_set_irq(void *opaque, int pirq, int level) diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h index 88233c3..11243e5 100644 --- a/include/hw/i386/ich9.h +++ b/include/hw/i386/ich9.h @@ -68,8 +68,7 @@ typedef struct ICH9LPCState { MemoryRegion rcrb_mem; /* root complex register block */ Notifier machine_ready; - qemu_irq *pic; - qemu_irq *ioapic; + qemu_irq *gsi; } ICH9LPCState; Object *ich9_lpc_find(void);