From patchwork Wed Jun 22 12:24:54 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Efimov Vasily X-Patchwork-Id: 9192671 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 931D5601C0 for ; Wed, 22 Jun 2016 12:39:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 834BB283E9 for ; Wed, 22 Jun 2016 12:39:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 77A4C283FE; Wed, 22 Jun 2016 12:39:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0E1B8283E9 for ; Wed, 22 Jun 2016 12:39:51 +0000 (UTC) Received: from localhost ([::1]:57973 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bFhRe-0002MP-4o for patchwork-qemu-devel@patchwork.kernel.org; Wed, 22 Jun 2016 08:39:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49835) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bFhE7-0003Pq-IH for qemu-devel@nongnu.org; Wed, 22 Jun 2016 08:25:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bFhE5-0001v4-Fu for qemu-devel@nongnu.org; Wed, 22 Jun 2016 08:25:50 -0400 Received: from smtp.ispras.ru ([83.149.199.79]:37778) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bFhDu-0001oN-1s; Wed, 22 Jun 2016 08:25:38 -0400 Received: from real.intra.ispras.ru (unknown [83.149.199.91]) by smtp.ispras.ru (Postfix) with ESMTP id C3FA22041C; Wed, 22 Jun 2016 15:25:06 +0300 (MSK) From: Efimov Vasily To: qemu-devel@nongnu.org Date: Wed, 22 Jun 2016 15:24:54 +0300 Message-Id: <1466598298-21214-11-git-send-email-real@ispras.ru> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1466598298-21214-1-git-send-email-real@ispras.ru> References: <1466598298-21214-1-git-send-email-real@ispras.ru> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 83.149.199.79 Subject: [Qemu-devel] [PATCH v2 10/14] ICH9 LPC: handle GSI as qdev GPIO X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Peter Maydell , Eduardo Habkost , qemu-block@nongnu.org, "Michael S. Tsirkin" , Markus Armbruster , Efimov Vasily , Max Reitz , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , Marcel Apfelbaum , Paolo Bonzini , Kirill Batuzov , John Snow , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The ICH9 LPC bridge has 24 output IRQs connected to GSI. Currently the IRQs are referenced by pointers. The pointers are initialized at startup by direct access to the structure fields. This violates Qemu device model. The patch makes the IRQs handling to use GPIO model. Signed-off-by: Efimov Vasily --- hw/i386/pc_q35.c | 6 +++++- hw/isa/lpc_ich9.c | 3 +++ include/hw/i386/ich9.h | 4 +++- 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 67bcede..d3213fd 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -60,6 +60,7 @@ static void pc_q35_init(MachineState *machine) PCIHostState *phb; PCIBus *host_bus; PCIDevice *lpc; + DeviceState *lpc_dev; BusState *idebus[MAX_SATA_PORTS]; ISADevice *rtc_state; MemoryRegion *system_io = get_system_io(); @@ -190,7 +191,10 @@ static void pc_q35_init(MachineState *machine) PC_MACHINE_ACPI_DEVICE_PROP, &error_abort); ich9_lpc = ICH9_LPC_DEVICE(lpc); - ich9_lpc->gsi = gsi; + lpc_dev = DEVICE(lpc); + for (i = 0; i < GSI_NUM_PINS; i++) { + qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, gsi[i]); + } pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, ICH9_LPC_NB_PIRQS); pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 7703357..36506ec 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -598,6 +598,7 @@ static void ich9_lpc_initfn(Object *obj) static void ich9_lpc_realize(PCIDevice *d, Error **errp) { ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); + DeviceState *dev = DEVICE(d); ISABus *isa_bus; isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), get_system_io(), @@ -625,6 +626,8 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp) memory_region_add_subregion_overlap(pci_address_space_io(d), ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem, 1); + + qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS); } static bool ich9_rst_cnt_needed(void *opaque) diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h index a09a445..c14490b 100644 --- a/include/hw/i386/ich9.h +++ b/include/hw/i386/ich9.h @@ -68,7 +68,7 @@ typedef struct ICH9LPCState { MemoryRegion rcrb_mem; /* root complex register block */ Notifier machine_ready; - qemu_irq *gsi; + qemu_irq gsi[GSI_NUM_PINS]; } ICH9LPCState; Object *ich9_lpc_find(void); @@ -176,6 +176,8 @@ Object *ich9_lpc_find(void); #define ICH9_LPC_PIC_NUM_PINS 16 #define ICH9_LPC_IOAPIC_NUM_PINS 24 +#define ICH9_GPIO_GSI "gsi" + /* D31:F2 SATA Controller #1 */ #define ICH9_SATA1_DEV 31 #define ICH9_SATA1_FUNC 2