From patchwork Wed Jun 22 12:24:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Efimov Vasily X-Patchwork-Id: 9192693 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A27C5601C0 for ; Wed, 22 Jun 2016 12:43:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 92D8028364 for ; Wed, 22 Jun 2016 12:43:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 87637283FE; Wed, 22 Jun 2016 12:43:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id F2D6A28364 for ; Wed, 22 Jun 2016 12:43:46 +0000 (UTC) Received: from localhost ([::1]:57991 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bFhVS-00066h-37 for patchwork-qemu-devel@patchwork.kernel.org; Wed, 22 Jun 2016 08:43:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49876) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bFhE9-0003SW-Gc for qemu-devel@nongnu.org; Wed, 22 Jun 2016 08:25:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bFhE3-0001uh-ST for qemu-devel@nongnu.org; Wed, 22 Jun 2016 08:25:52 -0400 Received: from smtp.ispras.ru ([83.149.199.79]:37790) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bFhDu-0001oR-6C; Wed, 22 Jun 2016 08:25:38 -0400 Received: from real.intra.ispras.ru (unknown [83.149.199.91]) by smtp.ispras.ru (Postfix) with ESMTP id 097D420426; Wed, 22 Jun 2016 15:25:07 +0300 (MSK) From: Efimov Vasily To: qemu-devel@nongnu.org Date: Wed, 22 Jun 2016 15:24:58 +0300 Message-Id: <1466598298-21214-15-git-send-email-real@ispras.ru> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1466598298-21214-1-git-send-email-real@ispras.ru> References: <1466598298-21214-1-git-send-email-real@ispras.ru> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 83.149.199.79 Subject: [Qemu-devel] [PATCH v2 14/14] ICH9 LPC: configure PCI IRQs routing internally X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Peter Maydell , Eduardo Habkost , qemu-block@nongnu.org, "Michael S. Tsirkin" , Markus Armbruster , Efimov Vasily , Max Reitz , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , Marcel Apfelbaum , Paolo Bonzini , Kirill Batuzov , John Snow , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP ICH9 LPC bridge is used to route PCI IRQs to GSI. The root PCI bus reference is required to setup the routing. According to specification, the bridge is connected to root bus. Hence, there is no reason to setup the routing externally. The patch moves the setup code to 'realize' method. Also several related functions are made static because they are no needed outside the bridge implementation any more. Signed-off-by: Efimov Vasily --- hw/i386/pc_q35.c | 3 --- hw/isa/lpc_ich9.c | 10 +++++++--- include/hw/i386/ich9.h | 3 --- 3 files changed, 7 insertions(+), 9 deletions(-) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 0f04c13..eca33b3 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -195,9 +195,6 @@ static void pc_q35_init(MachineState *machine) for (i = 0; i < GSI_NUM_PINS; i++) { qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, gsi[i]); } - pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, - ICH9_LPC_NB_PIRQS); - pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); isa_bus = ich9_lpc->isa_bus; if (kvm_pic_in_kernel()) { diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index c351351..7a0a0b0 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -253,7 +253,7 @@ static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi) qemu_set_irq(lpc->gsi[gsi], level); } -void ich9_lpc_set_irq(void *opaque, int pirq, int level) +static void ich9_lpc_set_irq(void *opaque, int pirq, int level) { ICH9LPCState *lpc = opaque; int pic_irq, pic_dis; @@ -269,7 +269,7 @@ void ich9_lpc_set_irq(void *opaque, int pirq, int level) /* return the pirq number (PIRQ[A-H]:0-7) corresponding to * a given device irq pin. */ -int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx) +static int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx) { BusState *bus = qdev_get_parent_bus(&pci_dev->qdev); PCIBus *pci_bus = PCI_BUS(bus); @@ -280,7 +280,7 @@ int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx) return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx]; } -PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin) +static PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin) { ICH9LPCState *lpc = opaque; PCIINTxRoute route; @@ -630,6 +630,10 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp) qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS); isa_bus_irqs(isa_bus, lpc->gsi); + + pci_bus_irqs(lpc->d.bus, ich9_lpc_set_irq, ich9_lpc_map_irq, lpc, + ICH9_LPC_NB_PIRQS); + pci_bus_set_route_irq_fn(lpc->d.bus, ich9_route_intx_pin_to_irq); } static bool ich9_rst_cnt_needed(void *opaque) diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h index c14490b..cd96841 100644 --- a/include/hw/i386/ich9.h +++ b/include/hw/i386/ich9.h @@ -14,9 +14,6 @@ #include "hw/acpi/ich9.h" #include "hw/pci/pci_bus.h" -void ich9_lpc_set_irq(void *opaque, int irq_num, int level); -int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx); -PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin); void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled); I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);