From patchwork Mon Jun 27 15:19:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 9200831 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 335A260757 for ; Mon, 27 Jun 2016 15:20:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 205AE28412 for ; Mon, 27 Jun 2016 15:20:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 11C2728594; Mon, 27 Jun 2016 15:20:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 74FD028412 for ; Mon, 27 Jun 2016 15:20:06 +0000 (UTC) Received: from localhost ([::1]:59287 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHYKT-0001ov-Gd for patchwork-qemu-devel@patchwork.kernel.org; Mon, 27 Jun 2016 11:20:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47440) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHYJu-0001mp-0d for qemu-devel@nongnu.org; Mon, 27 Jun 2016 11:19:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bHYJt-0001GG-3V for qemu-devel@nongnu.org; Mon, 27 Jun 2016 11:19:29 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:46032) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHYJs-0001G6-Tb for qemu-devel@nongnu.org; Mon, 27 Jun 2016 11:19:29 -0400 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Forcepoint Email with ESMTPS id 58CE98B9DBE45; Mon, 27 Jun 2016 16:19:24 +0100 (IST) Received: from hhmipssw204.hh.imgtec.org (10.100.21.121) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.294.0; Mon, 27 Jun 2016 16:19:27 +0100 From: Leon Alrae To: Date: Mon, 27 Jun 2016 16:19:11 +0100 Message-ID: <1467040752-18666-4-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1467040752-18666-1-git-send-email-leon.alrae@imgtec.com> References: <1467040752-18666-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.21.121] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PATCH 3/4] target-mips: support CP0.Config4.AE bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Hogan , Paul Burton , aurelien@aurel32.net Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Paul Burton The read-only Config4.AE bit set denotes extended 10 bits ASID. Signed-off-by: Paul Burton Signed-off-by: James Hogan Signed-off-by: Leon Alrae --- target-mips/cpu.h | 1 + target-mips/translate.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 62a149e..3a4720d 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -468,6 +468,7 @@ struct CPUMIPSState { int32_t CP0_Config4_rw_bitmask; #define CP0C4_M 31 #define CP0C4_IE 29 +#define CP0C4_AE 28 #define CP0C4_KScrExist 16 #define CP0C4_MMUExtDef 14 #define CP0C4_FTLBPageSize 8 diff --git a/target-mips/translate.c b/target-mips/translate.c index 01510b3..bab52cb 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -20302,7 +20302,8 @@ void cpu_state_reset(CPUMIPSState *env) if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) { env->CP0_CMGCRBase = 0x1fbf8000 >> 4; } - env->CP0_EntryHi_ASID_mask = 0xff; + env->CP0_EntryHi_ASID_mask = (env->CP0_Config4 & (1 << CP0C4_AE)) ? + 0x3ff : 0xff; env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); /* vectored interrupts not implemented, timer on int 7, no performance counters. */