| Message ID | 1467745398-28183-4-git-send-email-dgilbert@redhat.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Jul 05, 2016 at 08:03:17PM +0100, Dr. David Alan Gilbert (git) wrote: > From: "Dr. David Alan Gilbert" <dgilbert@redhat.com> > > Fill the bits between 51..number-of-physical-address-bits in the > MTRR_PHYSMASKn variable range mtrr masks so that they're consistent > in the migration stream irrespective of the physical address space > of the source VM in a migration. > > Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> > Suggested-by: Paolo Bonzini <pbonzini@redhat.com> [...] > @@ -2084,6 +2085,28 @@ static int kvm_get_msrs(X86CPU *cpu) > } > > assert(ret == cpu->kvm_msr_buf->nmsrs); > + /* > + * MTRR masks: Each mask consists of 5 parts > + * a 10..0: must be zero > + * b 11 : valid bit > + * c n-1.12: actual mask bits > + * d 51..n: reserved must be zero > + * e 63.52: reserved must be zero > + * > + * 'n' is the number of physical bits supported by the CPU and is > + * apparently always <= 52. We know our 'n' but don't know what > + * the destinations 'n' is; it might be smaller, in which case > + * it masks (c) on loading. It might be larger, in which case > + * we fill 'd' so that d..c is consistent irrespetive of the 'n' > + * we're migrating to. > + */ > + if (cpu->fill_mtrr_mask && cpu->phys_bits < TARGET_PHYS_ADDR_SPACE_BITS) { As we already ensure phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS in patch 1/4, what about just doing this: assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS) > + mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, > + TARGET_PHYS_ADDR_SPACE_BITS - cpu->phys_bits); What's the actual meaning of TARGET_PHYS_ADDR_SPACE_BITS? Can it ever change in the future? Should a change in TARGET_PHYS_ADDR_SPACE_BITS really change the migration format? To make sure we won't have any surprises if TARGET_PHYS_ADDR_SPACE_BITS change, I would change the code to: QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52); assert(cpu->phs_bits <= TARGET_PHYS_ADDR_SPACE_BITS); mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits); > + } else { > + mtrr_top_bits = 0; > + } > + > for (i = 0; i < ret; i++) { > uint32_t index = msrs[i].index; > switch (index) { > @@ -2279,7 +2302,8 @@ static int kvm_get_msrs(X86CPU *cpu) > break; > case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1): > if (index & 1) { > - env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data; > + env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data | > + mtrr_top_bits; > } else { > env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data; > } > -- > 2.7.4 >
* Eduardo Habkost (ehabkost@redhat.com) wrote: > On Tue, Jul 05, 2016 at 08:03:17PM +0100, Dr. David Alan Gilbert (git) wrote: > > From: "Dr. David Alan Gilbert" <dgilbert@redhat.com> > > > > Fill the bits between 51..number-of-physical-address-bits in the > > MTRR_PHYSMASKn variable range mtrr masks so that they're consistent > > in the migration stream irrespective of the physical address space > > of the source VM in a migration. > > > > Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> > > Suggested-by: Paolo Bonzini <pbonzini@redhat.com> > [...] > > @@ -2084,6 +2085,28 @@ static int kvm_get_msrs(X86CPU *cpu) > > } > > > > assert(ret == cpu->kvm_msr_buf->nmsrs); > > + /* > > + * MTRR masks: Each mask consists of 5 parts > > + * a 10..0: must be zero > > + * b 11 : valid bit > > + * c n-1.12: actual mask bits > > + * d 51..n: reserved must be zero > > + * e 63.52: reserved must be zero > > + * > > + * 'n' is the number of physical bits supported by the CPU and is > > + * apparently always <= 52. We know our 'n' but don't know what > > + * the destinations 'n' is; it might be smaller, in which case > > + * it masks (c) on loading. It might be larger, in which case > > + * we fill 'd' so that d..c is consistent irrespetive of the 'n' > > + * we're migrating to. > > + */ > > + if (cpu->fill_mtrr_mask && cpu->phys_bits < TARGET_PHYS_ADDR_SPACE_BITS) { > > As we already ensure phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS in > patch 1/4, what about just doing this: > > assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS) > > > > + mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, > > + TARGET_PHYS_ADDR_SPACE_BITS - cpu->phys_bits); > > What's the actual meaning of TARGET_PHYS_ADDR_SPACE_BITS? Can it > ever change in the future? Should a change in > TARGET_PHYS_ADDR_SPACE_BITS really change the migration format? > > To make sure we won't have any surprises if > TARGET_PHYS_ADDR_SPACE_BITS change, I would change the code to: > > QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52); > assert(cpu->phs_bits <= TARGET_PHYS_ADDR_SPACE_BITS); > mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits); Done. All limits tend to stretch with time, so no it wouldn't surprise me if that happened some day. Dave > > > > + } else { > > + mtrr_top_bits = 0; > > + } > > + > > for (i = 0; i < ret; i++) { > > uint32_t index = msrs[i].index; > > switch (index) { > > @@ -2279,7 +2302,8 @@ static int kvm_get_msrs(X86CPU *cpu) > > break; > > case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1): > > if (index & 1) { > > - env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data; > > + env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data | > > + mtrr_top_bits; > > } else { > > env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data; > > } > > -- > > 2.7.4 > > > > -- > Eduardo -- Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 7e43b20..d85e924 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -374,6 +374,11 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); .driver = TYPE_X86_CPU,\ .property = "cpuid-0xb",\ .value = "off",\ + },\ + {\ + .driver = TYPE_X86_CPU,\ + .property = "fill-mtrr-mask",\ + .value = "off",\ }, #define PC_COMPAT_2_5 \ diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 74d53c5..f33cf58 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -3282,6 +3282,7 @@ static Property x86_cpu_properties[] = { DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 9999), + DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, 0), DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0), DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0), diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 221b1a2..a9bbd91 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -1181,6 +1181,9 @@ struct X86CPU { /* Compatibility bits for old machine types: */ bool enable_cpuid_0xb; + /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ + bool fill_mtrr_mask; + /* Number of physical address bits supported */ uint32_t phys_bits; diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 6429205..b711867 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -1935,6 +1935,7 @@ static int kvm_get_msrs(X86CPU *cpu) CPUX86State *env = &cpu->env; struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries; int ret, i; + uint64_t mtrr_top_bits; kvm_msr_buf_reset(cpu); @@ -2084,6 +2085,28 @@ static int kvm_get_msrs(X86CPU *cpu) } assert(ret == cpu->kvm_msr_buf->nmsrs); + /* + * MTRR masks: Each mask consists of 5 parts + * a 10..0: must be zero + * b 11 : valid bit + * c n-1.12: actual mask bits + * d 51..n: reserved must be zero + * e 63.52: reserved must be zero + * + * 'n' is the number of physical bits supported by the CPU and is + * apparently always <= 52. We know our 'n' but don't know what + * the destinations 'n' is; it might be smaller, in which case + * it masks (c) on loading. It might be larger, in which case + * we fill 'd' so that d..c is consistent irrespetive of the 'n' + * we're migrating to. + */ + if (cpu->fill_mtrr_mask && cpu->phys_bits < TARGET_PHYS_ADDR_SPACE_BITS) { + mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, + TARGET_PHYS_ADDR_SPACE_BITS - cpu->phys_bits); + } else { + mtrr_top_bits = 0; + } + for (i = 0; i < ret; i++) { uint32_t index = msrs[i].index; switch (index) { @@ -2279,7 +2302,8 @@ static int kvm_get_msrs(X86CPU *cpu) break; case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1): if (index & 1) { - env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data; + env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data | + mtrr_top_bits; } else { env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data; }