From patchwork Thu Jul 7 14:50:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bharata B Rao X-Patchwork-Id: 9219079 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A90F66048B for ; Thu, 7 Jul 2016 14:51:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9531327DB3 for ; Thu, 7 Jul 2016 14:51:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 802A127DCD; Thu, 7 Jul 2016 14:51:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8A25727DB3 for ; Thu, 7 Jul 2016 14:51:22 +0000 (UTC) Received: from localhost ([::1]:40403 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bLAe9-00015d-LC for patchwork-qemu-devel@patchwork.kernel.org; Thu, 07 Jul 2016 10:51:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51695) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bLAdZ-00010u-9h for qemu-devel@nongnu.org; Thu, 07 Jul 2016 10:50:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bLAdW-0007Mt-4l for qemu-devel@nongnu.org; Thu, 07 Jul 2016 10:50:45 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:45277 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bLAdV-0007Mh-SB for qemu-devel@nongnu.org; Thu, 07 Jul 2016 10:50:42 -0400 Received: from pps.filterd (m0098414.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id u67En6vW015656 for ; Thu, 7 Jul 2016 10:50:41 -0400 Received: from e23smtp07.au.ibm.com (e23smtp07.au.ibm.com [202.81.31.140]) by mx0b-001b2d01.pphosted.com with ESMTP id 2415xmq17w-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 07 Jul 2016 10:50:41 -0400 Received: from localhost by e23smtp07.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 8 Jul 2016 00:50:34 +1000 X-IBM-Helo: d23dlp01.au.ibm.com X-IBM-MailFrom: bharata@linux.vnet.ibm.com X-IBM-RcptTo: qemu-devel@nongnu.org;qemu-ppc@nongnu.org Received: from d23relay10.au.ibm.com (d23relay10.au.ibm.com [9.190.26.77]) by d23dlp01.au.ibm.com (Postfix) with ESMTP id 27C772CE8054; Fri, 8 Jul 2016 00:50:34 +1000 (EST) Received: from d23av03.au.ibm.com (d23av03.au.ibm.com [9.190.234.97]) by d23relay10.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id u67EoYEU6816040; Fri, 8 Jul 2016 00:50:34 +1000 Received: from d23av03.au.ibm.com (localhost [127.0.0.1]) by d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id u67EoX0q019039; Fri, 8 Jul 2016 00:50:33 +1000 Received: from bharata.in.ibm.com ([9.77.202.64]) by d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id u67EoRp2018946; Fri, 8 Jul 2016 00:50:31 +1000 From: Bharata B Rao To: qemu-devel@nongnu.org Date: Thu, 7 Jul 2016 20:20:21 +0530 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1467903025-13383-1-git-send-email-bharata@linux.vnet.ibm.com> References: <1467903025-13383-1-git-send-email-bharata@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16070714-0044-0000-0000-000001BF2D7D X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 16070714-0045-0000-0000-00000514ABBD Message-Id: <1467903025-13383-2-git-send-email-bharata@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2016-07-07_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=3 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1604210000 definitions=main-1607070136 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [RFC PATCH v2 1/5] cpu, target-ppc: Move cpu_vmstate_[un]register calls to cpu_common_[un]realize X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nikunj@linux.vnet.ibm.com, Bharata B Rao , groug@kaod.org, qemu-ppc@nongnu.org, pbonzini@redhat.com, imammedo@redhat.com, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Move vmstate_register() call to cpu_common_realize(). Introduce cpu_common_unrealize() and move vmstate_unregister() to it. Change those archs that implement their own CPU unrealize routine to mandatorily call CPUClass::unrealize(). TODO: Decide if we indeed want to move vmstate_[un]register() calls to cpu_common_[un]realize(). Signed-off-by: Bharata B Rao Reviewed-by: David Gibson --- exec.c | 53 ++++++++++++++++++++++++++++----------------- include/qom/cpu.h | 2 ++ qom/cpu.c | 7 ++++++ target-ppc/cpu-qom.h | 2 ++ target-ppc/translate_init.c | 3 +++ 5 files changed, 47 insertions(+), 20 deletions(-) diff --git a/exec.c b/exec.c index 0122ef7..fb73910 100644 --- a/exec.c +++ b/exec.c @@ -594,9 +594,7 @@ AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx) /* Return the AddressSpace corresponding to the specified index */ return cpu->cpu_ases[asidx].as; } -#endif -#ifndef CONFIG_USER_ONLY static DECLARE_BITMAP(cpu_index_map, MAX_CPUMASK_BITS); static int cpu_get_free_index(Error **errp) @@ -617,6 +615,31 @@ static void cpu_release_index(CPUState *cpu) { bitmap_clear(cpu_index_map, cpu->cpu_index, 1); } + +void cpu_vmstate_register(CPUState *cpu) +{ + CPUClass *cc = CPU_GET_CLASS(cpu); + + if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { + vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); + } + if (cc->vmsd != NULL) { + vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu); + } +} + +void cpu_vmstate_unregister(CPUState *cpu) +{ + CPUClass *cc = CPU_GET_CLASS(cpu); + + if (cc->vmsd != NULL) { + vmstate_unregister(NULL, cc->vmsd, cpu); + } + if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { + vmstate_unregister(NULL, &vmstate_cpu_common, cpu); + } +} + #else static int cpu_get_free_index(Error **errp) @@ -634,12 +657,18 @@ static void cpu_release_index(CPUState *cpu) { return; } + +void cpu_vmstate_register(CPUState *cpu) +{ +} + +void cpu_vmstate_unregister(CPUState *cpu) +{ +} #endif void cpu_exec_exit(CPUState *cpu) { - CPUClass *cc = CPU_GET_CLASS(cpu); - #if defined(CONFIG_USER_ONLY) cpu_list_lock(); #endif @@ -657,18 +686,10 @@ void cpu_exec_exit(CPUState *cpu) #if defined(CONFIG_USER_ONLY) cpu_list_unlock(); #endif - - if (cc->vmsd != NULL) { - vmstate_unregister(NULL, cc->vmsd, cpu); - } - if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { - vmstate_unregister(NULL, &vmstate_cpu_common, cpu); - } } void cpu_exec_init(CPUState *cpu, Error **errp) { - CPUClass *cc = CPU_GET_CLASS(cpu); Error *local_err = NULL; cpu->as = NULL; @@ -705,15 +726,7 @@ void cpu_exec_init(CPUState *cpu, Error **errp) } QTAILQ_INSERT_TAIL(&cpus, cpu, node); #if defined(CONFIG_USER_ONLY) - (void) cc; cpu_list_unlock(); -#else - if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { - vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); - } - if (cc->vmsd != NULL) { - vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu); - } #endif } diff --git a/include/qom/cpu.h b/include/qom/cpu.h index cacb100..331386f 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -870,4 +870,6 @@ extern const struct VMStateDescription vmstate_cpu_common; .offset = 0, \ } +void cpu_vmstate_register(CPUState *cpu); +void cpu_vmstate_unregister(CPUState *cpu); #endif diff --git a/qom/cpu.c b/qom/cpu.c index a9727a1..1095ea1 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -325,10 +325,16 @@ static void cpu_common_parse_features(const char *typename, char *features, } } +static void cpu_common_unrealizefn(DeviceState *dev, Error **errp) +{ + cpu_vmstate_unregister(CPU(dev)); +} + static void cpu_common_realizefn(DeviceState *dev, Error **errp) { CPUState *cpu = CPU(dev); + cpu_vmstate_register(cpu); if (dev->hotplugged) { cpu_synchronize_post_init(cpu); cpu_resume(cpu); @@ -382,6 +388,7 @@ static void cpu_class_init(ObjectClass *klass, void *data) k->cpu_exec_exit = cpu_common_noop; k->cpu_exec_interrupt = cpu_common_exec_interrupt; dc->realize = cpu_common_realizefn; + dc->unrealize = cpu_common_unrealizefn; /* * Reason: CPUs still need special care by board code: wiring up * IRQs, adding reset handlers, halting non-first CPUs, ... diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h index 2864105..6ec2fca 100644 --- a/target-ppc/cpu-qom.h +++ b/target-ppc/cpu-qom.h @@ -163,6 +163,7 @@ struct ppc_segment_page_sizes; /** * PowerPCCPUClass: * @parent_realize: The parent class' realize handler. + * @parent_unrealize: The parent class' unrealize handler. * @parent_reset: The parent class' reset handler. * * A PowerPC CPU model. @@ -173,6 +174,7 @@ typedef struct PowerPCCPUClass { /*< public >*/ DeviceRealize parent_realize; + DeviceUnrealize parent_unrealize; void (*parent_reset)(CPUState *cpu); uint32_t pvr; diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 976a38b..bc8b767 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -9743,10 +9743,12 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp) static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp) { PowerPCCPU *cpu = POWERPC_CPU(dev); + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); CPUPPCState *env = &cpu->env; opc_handler_t **table; int i, j; + pcc->parent_unrealize(dev, errp); cpu_exec_exit(CPU(dev)); for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { @@ -10329,6 +10331,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) DeviceClass *dc = DEVICE_CLASS(oc); pcc->parent_realize = dc->realize; + pcc->parent_unrealize = dc->unrealize; pcc->pvr_match = ppc_pvr_match_default; pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always; dc->realize = ppc_cpu_realizefn;