From patchwork Tue Jul 12 14:31:19 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Markus Armbruster X-Patchwork-Id: 9225553 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A4D396086B for ; Tue, 12 Jul 2016 14:50:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9551427D85 for ; Tue, 12 Jul 2016 14:50:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 884E127F46; Tue, 12 Jul 2016 14:50:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B06D727D85 for ; Tue, 12 Jul 2016 14:50:27 +0000 (UTC) Received: from localhost ([::1]:41004 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bMz10-0003Eg-Ps for patchwork-qemu-devel@patchwork.kernel.org; Tue, 12 Jul 2016 10:50:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43955) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bMyiu-00037N-Tm for qemu-devel@nongnu.org; Tue, 12 Jul 2016 10:31:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bMyip-0001j4-F9 for qemu-devel@nongnu.org; Tue, 12 Jul 2016 10:31:43 -0400 Received: from mx1.redhat.com ([209.132.183.28]:50655) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bMyip-0001iW-6H for qemu-devel@nongnu.org; Tue, 12 Jul 2016 10:31:39 -0400 Received: from int-mx13.intmail.prod.int.phx2.redhat.com (int-mx13.intmail.prod.int.phx2.redhat.com [10.5.11.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id A8C3A1176DB for ; Tue, 12 Jul 2016 14:31:37 +0000 (UTC) Received: from blackfin.pond.sub.org (ovpn-116-29.ams2.redhat.com [10.36.116.29]) by int-mx13.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u6CEVZMr016593 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO) for ; Tue, 12 Jul 2016 10:31:36 -0400 Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 866B911386DA; Tue, 12 Jul 2016 16:31:34 +0200 (CEST) From: Markus Armbruster To: qemu-devel@nongnu.org Date: Tue, 12 Jul 2016 16:31:19 +0200 Message-Id: <1468333894-419-4-git-send-email-armbru@redhat.com> In-Reply-To: <1468333894-419-1-git-send-email-armbru@redhat.com> References: <1468333894-419-1-git-send-email-armbru@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.26 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Tue, 12 Jul 2016 14:31:37 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 03/18] target-*: Clean up cpu.h header guards X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Most of them use guard symbols like CPU_$target_H, but we also have __MIPS_CPU_H__ and __TRICORE_CPU_H__. They all upset scripts/clean-header-guards.pl. The script dislikes CPU_$target_H because they don't match their file name (they should, to make guard collisions less likely). The others are reserved identifiers. Clean them all up: use guard symbol $target_CPU_H for target-$target/cpu.h. Signed-off-by: Markus Armbruster Reviewed-by: Richard Henderson --- target-alpha/cpu.h | 6 +++--- target-arm/cpu.h | 4 ++-- target-cris/cpu.h | 5 +++-- target-i386/cpu.h | 7 ++++--- target-lm32/cpu.h | 4 ++-- target-m68k/cpu.h | 5 +++-- target-microblaze/cpu.h | 5 +++-- target-mips/cpu.h | 6 +++--- target-moxie/cpu.h | 7 ++++--- target-openrisc/cpu.h | 6 +++--- target-ppc/cpu.h | 7 ++++--- target-s390x/cpu.h | 5 +++-- target-sh4/cpu.h | 7 ++++--- target-sparc/cpu.h | 4 ++-- target-tilegx/cpu.h | 5 +++-- target-tricore/cpu.h | 7 ++++--- target-unicore32/cpu.h | 7 ++++--- target-xtensa/cpu.h | 4 ++-- 18 files changed, 56 insertions(+), 45 deletions(-) diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index 791da3b..ac5e801 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -17,8 +17,8 @@ * License along with this library; if not, see . */ -#if !defined (__CPU_ALPHA_H__) -#define __CPU_ALPHA_H__ +#ifndef ALPHA_CPU_H +#define ALPHA_CPU_H #include "qemu-common.h" #include "cpu-qom.h" @@ -524,4 +524,4 @@ static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc, *pflags = flags; } -#endif /* !defined (__CPU_ALPHA_H__) */ +#endif /* ALPHA_CPU_H */ diff --git a/target-arm/cpu.h b/target-arm/cpu.h index e2fac46..76d824d 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -16,9 +16,9 @@ * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, see . */ -#ifndef CPU_ARM_H -#define CPU_ARM_H +#ifndef ARM_CPU_H +#define ARM_CPU_H #include "kvm-consts.h" diff --git a/target-cris/cpu.h b/target-cris/cpu.h index e6046d2..7d7fe6e 100644 --- a/target-cris/cpu.h +++ b/target-cris/cpu.h @@ -17,8 +17,9 @@ * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, see . */ -#ifndef CPU_CRIS_H -#define CPU_CRIS_H + +#ifndef CRIS_CPU_H +#define CRIS_CPU_H #include "qemu-common.h" #include "cpu-qom.h" diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 5c7a279..776efe6 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -16,8 +16,9 @@ * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, see . */ -#ifndef CPU_I386_H -#define CPU_I386_H + +#ifndef I386_CPU_H +#define I386_CPU_H #include "qemu-common.h" #include "cpu-qom.h" @@ -1607,4 +1608,4 @@ void x86_cpu_dump_local_apic_state(CPUState *cs, FILE *f, /* cpu.c */ bool cpu_is_bsp(X86CPU *cpu); -#endif /* CPU_I386_H */ +#endif /* I386_CPU_H */ diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h index 4efe98d..d8a3515 100644 --- a/target-lm32/cpu.h +++ b/target-lm32/cpu.h @@ -17,8 +17,8 @@ * License along with this library; if not, see . */ -#ifndef CPU_LM32_H -#define CPU_LM32_H +#ifndef LM32_CPU_H +#define LM32_CPU_H #define TARGET_LONG_BITS 32 diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h index 9087769..b2faa6b 100644 --- a/target-m68k/cpu.h +++ b/target-m68k/cpu.h @@ -17,8 +17,9 @@ * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, see . */ -#ifndef CPU_M68K_H -#define CPU_M68K_H + +#ifndef M68K_CPU_H +#define M68K_CPU_H #define TARGET_LONG_BITS 32 diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index 16815df..beb75ff 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -16,8 +16,9 @@ * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, see . */ -#ifndef CPU_MICROBLAZE_H -#define CPU_MICROBLAZE_H + +#ifndef MICROBLAZE_CPU_H +#define MICROBLAZE_CPU_H #include "qemu-common.h" #include "cpu-qom.h" diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 9c4fc81..5182dc7 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -1,5 +1,5 @@ -#if !defined (__MIPS_CPU_H__) -#define __MIPS_CPU_H__ +#ifndef MIPS_CPU_H +#define MIPS_CPU_H //#define DEBUG_OP @@ -1066,4 +1066,4 @@ static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, do_raise_exception_err(env, exception, 0, pc); } -#endif /* !defined (__MIPS_CPU_H__) */ +#endif /* MIPS_CPU_H */ diff --git a/target-moxie/cpu.h b/target-moxie/cpu.h index 63d5caf..3e880fa 100644 --- a/target-moxie/cpu.h +++ b/target-moxie/cpu.h @@ -16,8 +16,9 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ -#ifndef _CPU_MOXIE_H -#define _CPU_MOXIE_H + +#ifndef MOXIE_CPU_H +#define MOXIE_CPU_H #include "qemu-common.h" @@ -139,4 +140,4 @@ static inline void cpu_get_tb_cpu_state(CPUMoxieState *env, target_ulong *pc, int moxie_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, int mmu_idx); -#endif /* _CPU_MOXIE_H */ +#endif /* MOXIE_CPU_H */ diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index 9451a7c..aaf1535 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -17,8 +17,8 @@ * License along with this library; if not, see . */ -#ifndef CPU_OPENRISC_H -#define CPU_OPENRISC_H +#ifndef OPENRISC_CPU_H +#define OPENRISC_CPU_H #define TARGET_LONG_BITS 32 @@ -408,4 +408,4 @@ static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0 -#endif /* CPU_OPENRISC_H */ +#endif /* OPENRISC_CPU_H */ diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 2666a3f..5fce1ff 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -16,8 +16,9 @@ * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, see . */ -#if !defined (__CPU_PPC_H__) -#define __CPU_PPC_H__ + +#ifndef PPC_CPU_H +#define PPC_CPU_H #include "qemu-common.h" @@ -2432,4 +2433,4 @@ int ppc_get_vcpu_dt_id(PowerPCCPU *cpu); PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id); void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len); -#endif /* !defined (__CPU_PPC_H__) */ +#endif /* PPC_CPU_H */ diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h index 0c8dba3..c216bda 100644 --- a/target-s390x/cpu.h +++ b/target-s390x/cpu.h @@ -19,8 +19,9 @@ * You should have received a copy of the GNU (Lesser) General Public * License along with this library; if not, see . */ -#ifndef CPU_S390X_H -#define CPU_S390X_H + +#ifndef S390X_CPU_H +#define S390X_CPU_H #include "qemu-common.h" #include "cpu-qom.h" diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index 3f9dae2..478ab55 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -16,8 +16,9 @@ * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, see . */ -#ifndef _CPU_SH4_H -#define _CPU_SH4_H + +#ifndef SH4_CPU_H +#define SH4_CPU_H #include "qemu-common.h" #include "cpu-qom.h" @@ -387,4 +388,4 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc, | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */ } -#endif /* _CPU_SH4_H */ +#endif /* SH4_CPU_H */ diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 604de84..15364a0 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -1,5 +1,5 @@ -#ifndef CPU_SPARC_H -#define CPU_SPARC_H +#ifndef SPARC_CPU_H +#define SPARC_CPU_H #include "qemu-common.h" #include "qemu/bswap.h" diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h index d740329..1735427 100644 --- a/target-tilegx/cpu.h +++ b/target-tilegx/cpu.h @@ -16,8 +16,9 @@ * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, see . */ -#ifndef CPU_TILEGX_H -#define CPU_TILEGX_H + +#ifndef TILEGX_CPU_H +#define TILEGX_CPU_H #include "qemu-common.h" diff --git a/target-tricore/cpu.h b/target-tricore/cpu.h index a298d63..a3493a1 100644 --- a/target-tricore/cpu.h +++ b/target-tricore/cpu.h @@ -16,8 +16,9 @@ * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, see . */ -#if !defined(__TRICORE_CPU_H__) -#define __TRICORE_CPU_H__ + +#ifndef TRICORE_CPU_H +#define TRICORE_CPU_H #include "tricore-defs.h" #include "qemu-common.h" @@ -420,4 +421,4 @@ int cpu_tricore_handle_mmu_fault(CPUState *cpu, target_ulong address, int rw, int mmu_idx); #define cpu_handle_mmu_fault cpu_tricore_handle_mmu_fault -#endif /*__TRICORE_CPU_H__ */ +#endif /* TRICORE_CPU_H */ diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h index 83f7584..7b5b405 100644 --- a/target-unicore32/cpu.h +++ b/target-unicore32/cpu.h @@ -8,8 +8,9 @@ * published by the Free Software Foundation, or (at your option) any * later version. See the COPYING file in the top-level directory. */ -#ifndef QEMU_UNICORE32_CPU_H -#define QEMU_UNICORE32_CPU_H + +#ifndef UNICORE32_CPU_H +#define UNICORE32_CPU_H #define TARGET_LONG_BITS 32 #define TARGET_PAGE_BITS 12 @@ -184,4 +185,4 @@ int uc32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, void uc32_translate_init(void); void switch_mode(CPUUniCore32State *, int); -#endif /* QEMU_UNICORE32_CPU_H */ +#endif /* UNICORE32_CPU_H */ diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index ce9fb5b..7fe82a3 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -25,8 +25,8 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef CPU_XTENSA_H -#define CPU_XTENSA_H +#ifndef XTENSA_CPU_H +#define XTENSA_CPU_H #define ALIGNED_ONLY #define TARGET_LONG_BITS 32