From patchwork Thu Jul 14 16:29:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 9230141 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 587176075D for ; Thu, 14 Jul 2016 16:30:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4A8DB281B7 for ; Thu, 14 Jul 2016 16:30:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3F73D28305; Thu, 14 Jul 2016 16:30:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A9568281B7 for ; Thu, 14 Jul 2016 16:30:29 +0000 (UTC) Received: from localhost ([::1]:55527 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bNjWu-0006kS-Ke for patchwork-qemu-devel@patchwork.kernel.org; Thu, 14 Jul 2016 12:30:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51648) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bNjWL-0006XY-0s for qemu-devel@nongnu.org; Thu, 14 Jul 2016 12:29:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bNjWJ-0002As-UW for qemu-devel@nongnu.org; Thu, 14 Jul 2016 12:29:52 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:58290) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bNjWJ-0002A6-NQ for qemu-devel@nongnu.org; Thu, 14 Jul 2016 12:29:51 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1bNjWG-0000LX-SS for qemu-devel@nongnu.org; Thu, 14 Jul 2016 17:29:48 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Jul 2016 17:29:43 +0100 Message-Id: <1468513783-25449-12-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1468513783-25449-1-git-send-email-peter.maydell@linaro.org> References: <1468513783-25449-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 11/11] ast2400: externalize revision numbers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Cédric Le Goater AST2400_A0_SILICON_REV is defined twice. Fix this by including the definition in the header file as well as the routine to check if a silicon revision is supported. It will useful to reuse in other controllers. Let's add also AST2500_A0_SILICON_REV for future use. Signed-off-by: Cédric Le Goater Message-id: 1467994016-11678-5-git-send-email-clg@kaod.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/ast2400.c | 2 -- hw/misc/aspeed_scu.c | 4 +--- include/hw/misc/aspeed_scu.h | 5 +++++ 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/arm/ast2400.c b/hw/arm/ast2400.c index 0555843..326fdb3 100644 --- a/hw/arm/ast2400.c +++ b/hw/arm/ast2400.c @@ -34,8 +34,6 @@ #define AST2400_FMC_FLASH_BASE 0x20000000 #define AST2400_SPI_FLASH_BASE 0x30000000 -#define AST2400_A0_SILICON_REV 0x02000303 - static const int uart_irqs[] = { 9, 32, 33, 34, 10 }; static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, }; diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index b61c05e..c7e2c82 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -88,8 +88,6 @@ #define PROT_KEY_UNLOCK 0x1688A8A8 #define SCU_IO_REGION_SIZE 0x20000 -#define AST2400_A0_SILICON_REV 0x02000303U - static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = { [SYS_RST_CTRL] = 0xFFCFFEDCU, [CLK_SEL] = 0xF3F40000U, @@ -212,7 +210,7 @@ static void aspeed_scu_reset(DeviceState *dev) static uint32_t aspeed_silicon_revs[] = { AST2400_A0_SILICON_REV, }; -static bool is_supported_silicon_rev(uint32_t silicon_rev) +bool is_supported_silicon_rev(uint32_t silicon_rev) { int i; diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index 6b8e46f..fdfd982 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -31,4 +31,9 @@ typedef struct AspeedSCUState { uint32_t hw_strap2; } AspeedSCUState; +#define AST2400_A0_SILICON_REV 0x02000303U +#define AST2500_A0_SILICON_REV 0x04000303U + +extern bool is_supported_silicon_rev(uint32_t silicon_rev); + #endif /* ASPEED_SCU_H */