| Message ID | 1470858179-27754-2-git-send-email-davidkiarie4@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 11.08.2016 00:42, David Kiarie wrote: > Introduce macros and trace events for use in AMD IOMMU > interrupt remapping > > Signed-off-by: David Kiarie <davidkiarie4@gmail.com> > --- > hw/i386/amd_iommu.h | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++++ > hw/i386/trace-events | 7 +++++ > 2 files changed, 79 insertions(+) > > diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h > index 5d0b91d..2a7f19e 100644 > --- a/hw/i386/amd_iommu.h > +++ b/hw/i386/amd_iommu.h > @@ -177,6 +177,78 @@ > #define AMDVI_IOTLB_MAX_SIZE 1024 > #define AMDVI_DEVID_SHIFT 36 > > +/* interrupt types */ > +#define AMDVI_MT_FIXED 0x0 > +#define AMDVI_MT_ARBIT 0x1 > +#define AMDVI_MT_SMI 0x2 > +#define AMDVI_MT_NMI 0x3 > +#define AMDVI_MT_INIT 0x4 > +#define AMDVI_MT_EXTINT 0x6 > +#define AMDVI_MT_LINT1 0xb > +#define AMDVI_MT_LINT0 0xe > + > +/* Ext reg, GA support */ > +#define AMDVI_GASUP (1UL << 7) > +/* MMIO control GA enable bits */ > +#define AMDVI_GAEN (1UL << 17) > + > +/* MSI interrupt type mask */ > +#define AMDVI_IR_TYPE_MASK 0x300 > + > +/* interrupt destination mode */ > +#define AMDVI_IRDEST_MODE_MASK 0x2 > + > +/* select MSI data 10:0 bits */ > +#define AMDVI_IRTE_INDEX_MASK 0x7ff > + > +/* bits determining whether specific interrupts should be passed > + * split DTE into 64-bit chunks > + */ > +#define AMDVI_DTE_INTPASS 56 > +#define AMDVI_DTE_EINTPASS 57 > +#define AMDVI_DTE_NMIPASS 58 > +#define AMDVI_DTE_INTCTL 60 > +#define AMDVI_DTE_LINT0PASS 62 > +#define AMDVI_DTE_LINT1PASS 63 I suggest adding _SHIFT prefix, to make the meaning clearer. > + > +/* interrupt data valid */ > +#define AMDVI_IR_VALID (1UL << 0) > + > +/* interrupt root table mask */ > +#define AMDVI_IRTEROOT_MASK 0xffffffffffffc0 > + > +/* default IRTE size */ > +#define AMDVI_DEFAULT_IRTE_SIZE 0x4 > + > +/* IRTE size with GASup enabled */ > +#define AMDVI_IRTE_SIZE_GASUP 0x10 We don't have Virtual APIC, and perhaps this is not needed (see comments in the next patch). > + > +#define AMDVI_IRTE_VECTOR_MASK (0xffU << 16) > +#define AMDVI_IRTE_DEST_MASK (0xffU << 8) > +#define AMDVI_IRTE_DM_MASK (0x1U << 6) > +#define AMDVI_IRTE_RQEOI_MASK (0x1U << 5) > +#define AMDVI_IRTE_INTTYPE_MASK (0x7U << 2) > +#define AMDVI_IRTE_SUPIOPF_MASK (0x1U << 1) > +#define AMDVI_IRTE_REMAP_MASK (0x1U << 0) > + > +#define AMDVI_IR_TABLE_SIZE_MASK 0xfe > + > +/* offsets into MSI data */ > +#define AMDVI_MSI_DATA_DM_RSHIFT 0x8 > +#define AMDVI_MSI_DATA_LEVEL_RSHIFT 0xe > +#define AMDVI_MSI_DATA_TRM_RSHIFT 0xf > + > +/* offsets into MSI address */ > +#define AMDVI_MSI_ADDR_DM_RSHIFT 0x2 > +#define AMDVI_MSI_ADDR_RH_RSHIFT 0x3 > +#define AMDVI_MSI_ADDR_DEST_RSHIFT 0xc > + > +#define AMDVI_BUS_NUM 0x0 > +/* AMD-Vi specific IOAPIC Device function */ > +#define AMDVI_DEVFN_IOAPIC 0xa0 So you decided not to keep these as a single AMDVI_SOUTHBRIDGE_IOAPIC_ID, or similar? Valentine > + > +#define AMDVI_LOCAL_APIC_ADDR 0xfee00000 > + > /* extended feature support */ > #define AMDVI_EXT_FEATURES (AMDVI_FEATURE_PREFETCH | AMDVI_FEATURE_PPR | \ > AMDVI_FEATURE_IA | AMDVI_FEATURE_GT | AMDVI_FEATURE_GA | \ > diff --git a/hw/i386/trace-events b/hw/i386/trace-events > index 592de3a..5c12c10 100644 > --- a/hw/i386/trace-events > +++ b/hw/i386/trace-events > @@ -42,3 +42,10 @@ amdvi_mode_invalid(unsigned level, uint64_t addr)"error: translation level 0x%"P > amdvi_page_fault(uint64_t addr) "error: page fault accessing guest physical address 0x%"PRIx64 > amdvi_iotlb_hit(uint16_t bus, uint16_t slot, uint16_t func, uint64_t addr, uint64_t txaddr) "hit iotlb devid %02x:%02x.%x gpa 0x%"PRIx64 " hpa 0x%"PRIx64 > amdvi_translation_result(uint16_t bus, uint16_t slot, uint16_t func, uint64_t addr, uint64_t txaddr) "devid: %02x:%02x.%x gpa 0x%"PRIx64 " hpa 0x%"PRIx64 > +amdvi_irte_get_fail(uint64_t addr, uint64_t offset) "couldn't access device table entry 0x%"PRIx64" + offset 0x%"PRIx64 > +amdvi_invalid_irte_entry(uint16_t devid, uint64_t offset) "devid %x requested IRTE offset 0x%"PRIx64" Outside IR table range" > +amdvi_ir_request(uint32_t data, uint64_t addr, uint16_t sid) "IR request data 0x%"PRIx32" address 0x%"PRIx64" SID %x" > +amdvi_ir_remap(uint32_t data, uint64_t addr, uint16_t sid) "IR remap data 0x%"PRIx32" address 0x%"PRIx64" SID %x" > +amdvi_ir_target_abort(uint32_t data, uint64_t addr, uint16_t sid) "IR target abort data 0x%"PRIx32" address 0x%"PRIx64" SID %x" > +amdvi_ir_write_fail(uint64_t addr, uint32_t data) "fail to write to addr 0x%"PRIx64 " value 0x%"PRIx32 > +amdvi_ir_read_fail(uint64_t addr) " fail to read from addr 0x%"PRIx64 >
diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index 5d0b91d..2a7f19e 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -177,6 +177,78 @@ #define AMDVI_IOTLB_MAX_SIZE 1024 #define AMDVI_DEVID_SHIFT 36 +/* interrupt types */ +#define AMDVI_MT_FIXED 0x0 +#define AMDVI_MT_ARBIT 0x1 +#define AMDVI_MT_SMI 0x2 +#define AMDVI_MT_NMI 0x3 +#define AMDVI_MT_INIT 0x4 +#define AMDVI_MT_EXTINT 0x6 +#define AMDVI_MT_LINT1 0xb +#define AMDVI_MT_LINT0 0xe + +/* Ext reg, GA support */ +#define AMDVI_GASUP (1UL << 7) +/* MMIO control GA enable bits */ +#define AMDVI_GAEN (1UL << 17) + +/* MSI interrupt type mask */ +#define AMDVI_IR_TYPE_MASK 0x300 + +/* interrupt destination mode */ +#define AMDVI_IRDEST_MODE_MASK 0x2 + +/* select MSI data 10:0 bits */ +#define AMDVI_IRTE_INDEX_MASK 0x7ff + +/* bits determining whether specific interrupts should be passed + * split DTE into 64-bit chunks + */ +#define AMDVI_DTE_INTPASS 56 +#define AMDVI_DTE_EINTPASS 57 +#define AMDVI_DTE_NMIPASS 58 +#define AMDVI_DTE_INTCTL 60 +#define AMDVI_DTE_LINT0PASS 62 +#define AMDVI_DTE_LINT1PASS 63 + +/* interrupt data valid */ +#define AMDVI_IR_VALID (1UL << 0) + +/* interrupt root table mask */ +#define AMDVI_IRTEROOT_MASK 0xffffffffffffc0 + +/* default IRTE size */ +#define AMDVI_DEFAULT_IRTE_SIZE 0x4 + +/* IRTE size with GASup enabled */ +#define AMDVI_IRTE_SIZE_GASUP 0x10 + +#define AMDVI_IRTE_VECTOR_MASK (0xffU << 16) +#define AMDVI_IRTE_DEST_MASK (0xffU << 8) +#define AMDVI_IRTE_DM_MASK (0x1U << 6) +#define AMDVI_IRTE_RQEOI_MASK (0x1U << 5) +#define AMDVI_IRTE_INTTYPE_MASK (0x7U << 2) +#define AMDVI_IRTE_SUPIOPF_MASK (0x1U << 1) +#define AMDVI_IRTE_REMAP_MASK (0x1U << 0) + +#define AMDVI_IR_TABLE_SIZE_MASK 0xfe + +/* offsets into MSI data */ +#define AMDVI_MSI_DATA_DM_RSHIFT 0x8 +#define AMDVI_MSI_DATA_LEVEL_RSHIFT 0xe +#define AMDVI_MSI_DATA_TRM_RSHIFT 0xf + +/* offsets into MSI address */ +#define AMDVI_MSI_ADDR_DM_RSHIFT 0x2 +#define AMDVI_MSI_ADDR_RH_RSHIFT 0x3 +#define AMDVI_MSI_ADDR_DEST_RSHIFT 0xc + +#define AMDVI_BUS_NUM 0x0 +/* AMD-Vi specific IOAPIC Device function */ +#define AMDVI_DEVFN_IOAPIC 0xa0 + +#define AMDVI_LOCAL_APIC_ADDR 0xfee00000 + /* extended feature support */ #define AMDVI_EXT_FEATURES (AMDVI_FEATURE_PREFETCH | AMDVI_FEATURE_PPR | \ AMDVI_FEATURE_IA | AMDVI_FEATURE_GT | AMDVI_FEATURE_GA | \ diff --git a/hw/i386/trace-events b/hw/i386/trace-events index 592de3a..5c12c10 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -42,3 +42,10 @@ amdvi_mode_invalid(unsigned level, uint64_t addr)"error: translation level 0x%"P amdvi_page_fault(uint64_t addr) "error: page fault accessing guest physical address 0x%"PRIx64 amdvi_iotlb_hit(uint16_t bus, uint16_t slot, uint16_t func, uint64_t addr, uint64_t txaddr) "hit iotlb devid %02x:%02x.%x gpa 0x%"PRIx64 " hpa 0x%"PRIx64 amdvi_translation_result(uint16_t bus, uint16_t slot, uint16_t func, uint64_t addr, uint64_t txaddr) "devid: %02x:%02x.%x gpa 0x%"PRIx64 " hpa 0x%"PRIx64 +amdvi_irte_get_fail(uint64_t addr, uint64_t offset) "couldn't access device table entry 0x%"PRIx64" + offset 0x%"PRIx64 +amdvi_invalid_irte_entry(uint16_t devid, uint64_t offset) "devid %x requested IRTE offset 0x%"PRIx64" Outside IR table range" +amdvi_ir_request(uint32_t data, uint64_t addr, uint16_t sid) "IR request data 0x%"PRIx32" address 0x%"PRIx64" SID %x" +amdvi_ir_remap(uint32_t data, uint64_t addr, uint16_t sid) "IR remap data 0x%"PRIx32" address 0x%"PRIx64" SID %x" +amdvi_ir_target_abort(uint32_t data, uint64_t addr, uint16_t sid) "IR target abort data 0x%"PRIx32" address 0x%"PRIx64" SID %x" +amdvi_ir_write_fail(uint64_t addr, uint32_t data) "fail to write to addr 0x%"PRIx64 " value 0x%"PRIx32 +amdvi_ir_read_fail(uint64_t addr) " fail to read from addr 0x%"PRIx64
Introduce macros and trace events for use in AMD IOMMU interrupt remapping Signed-off-by: David Kiarie <davidkiarie4@gmail.com> --- hw/i386/amd_iommu.h | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++++ hw/i386/trace-events | 7 +++++ 2 files changed, 79 insertions(+)