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[V2,3/6] hw/iommu: Prepare for AMD IOMMU interrupt remapping

Message ID 1471278766-25277-4-git-send-email-davidkiarie4@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

David Kiarie Aug. 15, 2016, 4:32 p.m. UTC 
Introduce macros and trace events for use in AMD IOMMU
interrupt remapping

Signed-off-by: David Kiarie <davidkiarie4@gmail.com>
---
 hw/i386/amd_iommu.h | 38 ++++++++++++++++----------------------
 1 file changed, 16 insertions(+), 22 deletions(-)
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Patch

diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h
index 2f4ac55..6f62e3a 100644
--- a/hw/i386/amd_iommu.h
+++ b/hw/i386/amd_iommu.h
@@ -187,11 +187,6 @@ 
 #define AMDVI_MT_LINT1  0xb
 #define AMDVI_MT_LINT0  0xe
 
-/* Ext reg, GA support */
-#define AMDVI_GASUP    (1UL << 7)
-/* MMIO control GA enable bits */
-#define AMDVI_GAEN     (1UL << 17)
-
 /* MSI interrupt type mask */
 #define AMDVI_IR_TYPE_MASK 0x300
 
@@ -204,12 +199,18 @@ 
 /* bits determining whether specific interrupts should be passed
  * split DTE into 64-bit chunks
  */
-#define AMDVI_DTE_INTPASS       56
-#define AMDVI_DTE_EINTPASS      57
-#define AMDVI_DTE_NMIPASS       58
-#define AMDVI_DTE_INTCTL        60
-#define AMDVI_DTE_LINT0PASS     62
-#define AMDVI_DTE_LINT1PASS     63
+#define AMDVI_DTE_INTPASS_LSHIFT       56
+#define AMDVI_DTE_EINTPASS_LSHIFT      57
+#define AMDVI_DTE_NMIPASS_LSHIFT       58
+#define AMDVI_DTE_INTCTL_RSHIFT        60
+#define AMDVI_DTE_LINT0PASS_LSHIFT     62
+#define AMDVI_DTE_LINT1PASS_LSHIFT     63
+
+/* INTCTL expected values */
+#define AMDVI_INTCTL_ABORT      0x0
+#define AMDVI_INTCTL_PASS       0x1
+#define AMDVI_INTCTL_REMAP      0x2
+#define AMDVI_INTCTL_RSVD       0x3
 
 /* interrupt data valid */
 #define AMDVI_IR_VALID          (1UL << 0)
@@ -220,17 +221,6 @@ 
 /* default IRTE size */
 #define AMDVI_DEFAULT_IRTE_SIZE 0x4
 
-/* IRTE size with GASup enabled */
-#define AMDVI_IRTE_SIZE_GASUP   0x10
-
-#define AMDVI_IRTE_VECTOR_MASK    (0xffU << 16)
-#define AMDVI_IRTE_DEST_MASK      (0xffU << 8)
-#define AMDVI_IRTE_DM_MASK        (0x1U << 6)
-#define AMDVI_IRTE_RQEOI_MASK     (0x1U << 5)
-#define AMDVI_IRTE_INTTYPE_MASK   (0x7U << 2)
-#define AMDVI_IRTE_SUPIOPF_MASK   (0x1U << 1)
-#define AMDVI_IRTE_REMAP_MASK     (0x1U << 0)
-
 #define AMDVI_IR_TABLE_SIZE_MASK 0xfe
 
 /* offsets into MSI data */
@@ -243,6 +233,10 @@ 
 #define AMDVI_MSI_ADDR_RH_RSHIFT       0x3
 #define AMDVI_MSI_ADDR_DEST_RSHIFT     0xc
 
+#define AMDVI_BUS_NUM                  0x0
+/* AMD-Vi specific IOAPIC Device function */
+#define AMDVI_DEVFN_IOAPIC             0xa0
+
 #define AMDVI_LOCAL_APIC_ADDR     0xfee00000
 
 /* extended feature support */