diff mbox

target-arm: Fix lpae bit in FSR on an alignment fault

Message ID 1471283293-169850-1-git-send-email-afarallax@yandex.ru (mailing list archive)
State New, archived
Headers show

Commit Message

Sergey Sorokin Aug. 15, 2016, 5:48 p.m. UTC 
If an alignment fault occurred and target EL is using AArch32,
then DFSR/IFSR bit LPAE[9] must be set correctly.

Signed-off-by: Sergey Sorokin <afarallax@yandex.ru>
---
 target-arm/op_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Peter Maydell Aug. 15, 2016, 6:06 p.m. UTC | #1 
On 15 August 2016 at 18:48, Sergey Sorokin <afarallax@yandex.ru> wrote:
> If an alignment fault occurred and target EL is using AArch32,
> then DFSR/IFSR bit LPAE[9] must be set correctly.
>
> Signed-off-by: Sergey Sorokin <afarallax@yandex.ru>
> ---
>  target-arm/op_helper.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
> index 3e8588e..be27b21 100644
> --- a/target-arm/op_helper.c
> +++ b/target-arm/op_helper.c
> @@ -194,7 +194,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
>       * the LPAE long descriptor format, or the short descriptor format
>       */
>      if (arm_s1_regime_using_lpae_format(env, cpu_mmu_index(env, false))) {
> -        env->exception.fsr = 0x21;
> +        env->exception.fsr = (1 << 9) | 0x21;
>      } else {
>          env->exception.fsr = 0x1;
>      }

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

I've applied this to the set of target-arm patches I'm collecting for 2.8.

thanks
-- PMM
diff mbox

Patch

diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 3e8588e..be27b21 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -194,7 +194,7 @@  void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
      * the LPAE long descriptor format, or the short descriptor format
      */
     if (arm_s1_regime_using_lpae_format(env, cpu_mmu_index(env, false))) {
-        env->exception.fsr = 0x21;
+        env->exception.fsr = (1 << 9) | 0x21;
     } else {
         env->exception.fsr = 0x1;
     }