diff mbox

[RFC,v2,10/12] q35: initialize MMCFG base when there is no firmware

Message ID 1472120105-29235-11-git-send-email-chao.p.peng@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Chao Peng Aug. 25, 2016, 10:15 a.m. UTC 
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
---
 hw/pci-host/q35.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)
diff mbox

Patch

diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index e33d5a5..c5c5fe2 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -448,9 +448,18 @@  static void mch_reset(DeviceState *qdev)
 {
     PCIDevice *d = PCI_DEVICE(qdev);
     MCHPCIState *mch = MCH_PCI_DEVICE(d);
+    PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
+    uint64_t pciexbar = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
 
-    pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR,
-                 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
+    if (!pcms->fw_cfg) {
+        pciexbar |= MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M;
+        pciexbar |= MCH_HOST_BRIDGE_PCIEXBAREN;
+
+        e820_add_entry(MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT,
+                       MCH_HOST_BRIDGE_PCIEXBAR_MAX, E820_RESERVED);
+    }
+
+    pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, pciexbar);
 
     d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
     d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT;
@@ -516,6 +525,8 @@  static void mch_realize(PCIDevice *d, Error **errp)
     init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory,
              mch->pci_address_space, &mch->pam_regions[1],
              PAM_EXPAN_BASE, 12 * PAM_EXPAN_SIZE);
+
+    mch_reset(DEVICE(mch));
 }
 
 uint64_t mch_mcfg_base(void)