From patchwork Mon Sep 5 14:02:08 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 9314083 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A1DB760760 for ; Mon, 5 Sep 2016 14:19:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 92E8628AC5 for ; Mon, 5 Sep 2016 14:19:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8799B28ACA; Mon, 5 Sep 2016 14:19:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B8F5928AC5 for ; Mon, 5 Sep 2016 14:19:24 +0000 (UTC) Received: from localhost ([::1]:54922 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bguk7-000579-GN for patchwork-qemu-devel@patchwork.kernel.org; Mon, 05 Sep 2016 10:19:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33697) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bguUV-0008TL-Ci for qemu-devel@nongnu.org; Mon, 05 Sep 2016 10:03:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bguUQ-0005WJ-FK for qemu-devel@nongnu.org; Mon, 05 Sep 2016 10:03:14 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:37397 helo=mail.rt-rk.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bguUQ-0005WB-7o for qemu-devel@nongnu.org; Mon, 05 Sep 2016 10:03:10 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 510081A4539; Mon, 5 Sep 2016 16:03:09 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from mcs19.ba.imgtec.org (unknown [82.117.201.26]) by mail.rt-rk.com (Postfix) with ESMTPSA id 33A971A1D91; Mon, 5 Sep 2016 16:03:09 +0200 (CEST) From: Aleksandar Markovic To: qemu-devel@nongnu.org, riku.voipio@iki.fi, peter.maydell@linaro.org, aurelien@aurel32.net, leon.alrae@imgtec.com, petar.jovanovic@imgtec.com, miodrag.dinic@imgtec.com, aleksandar.rikalo@imgtec.com, aleksandar.markovic@imgtec.com Date: Mon, 5 Sep 2016 16:02:08 +0200 Message-Id: <1473084137-35485-6-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1473084137-35485-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1473084137-35485-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v4 5/5] linux-user: Fix certain argument alignment cases for Mips64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Aleksandar Markovic The function that is changed in this patch is supposed to indicate that there was certaing argument rearangement related to 64-bit arguments on 32-bit platforms. The background on such rearangements can be found, for example, in the man page for syscall(2). However, for 64-bit Mips architectures there is no such rearangement, and this patch reflects it. Signed-off-by: Aleksandar Rikalo --- linux-user/syscall.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 908f114..6ac669f 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -622,7 +622,13 @@ static inline int regpairs_aligned(void *cpu_env) { return ((((CPUARMState *)cpu_env)->eabi) == 1) ; } #elif defined(TARGET_MIPS) -static inline int regpairs_aligned(void *cpu_env) { return 1; } +static inline int regpairs_aligned(void *cpu_env) { +#if TARGET_ABI_BITS == 32 + return 1; +#else + return 0; +#endif +} #elif defined(TARGET_PPC) && !defined(TARGET_PPC64) /* SysV AVI for PPC32 expects 64bit parameters to be passed on odd/even pairs * of registers which translates to the same as ARM/MIPS, because we start with