From patchwork Tue Sep 6 03:40:14 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 9315451 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 10CBB60760 for ; Tue, 6 Sep 2016 03:49:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0351428B30 for ; Tue, 6 Sep 2016 03:49:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EC45C28B32; Tue, 6 Sep 2016 03:49:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9FDA628B30 for ; Tue, 6 Sep 2016 03:49:21 +0000 (UTC) Received: from localhost ([::1]:58165 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bh7Nw-0001GN-DG for patchwork-qemu-devel@patchwork.kernel.org; Mon, 05 Sep 2016 23:49:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48277) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bh7E8-0000uZ-0l for qemu-devel@nongnu.org; Mon, 05 Sep 2016 23:39:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bh7E2-00076W-Ph for qemu-devel@nongnu.org; Mon, 05 Sep 2016 23:39:11 -0400 Received: from ozlabs.org ([103.22.144.67]:59265) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bh7E2-0006zO-4J; Mon, 05 Sep 2016 23:39:06 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 3sSslN5Tdxz9vDS; Tue, 6 Sep 2016 13:38:52 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1473133136; bh=CjtQvjOHEqzrV6VTUTcCmDbiJPd6jfi4NQEPi4aAU1E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QhYqaiKr2vDjzPkSxgqMYY00GWqMLlVUZ7iDXoSvzSsX9/kGRYGQ450okW+2FaeJf GqxjdgZboLU+B6u9794K5BVDharcA5PmEVT6HE4ruFGk2HG9cPpD9b46pBiQOyoxys Y2qqZ7FCLaA1s4l0t/6R5ZFJWWKILtjKPhgeRvEI= From: David Gibson To: peter.maydell@linearo.org Date: Tue, 6 Sep 2016 13:40:14 +1000 Message-Id: <1473133253-17598-28-git-send-email-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1473133253-17598-1-git-send-email-david@gibson.dropbear.id.au> References: <1473133253-17598-1-git-send-email-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PULL 27/66] ppc: Don't update NIP in lswi/lswx/stswi/stswx X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Gibson , qemu-ppc@nongnu.org, agraf@suse.de, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Benjamin Herrenschmidt Instead, pass GETPC() result to the corresponding helpers. This requires a bit of fiddling to get the PC (hopefully) right in the case where we generate a program check, though the hacks there are temporary, a subsequent patch will clean this all up by always having the nip already set to the right instruction when taking the fault. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/excp_helper.c | 8 ++++++++ target-ppc/mem_helper.c | 26 ++++++++++++++++---------- target-ppc/translate.c | 18 ++++++++---------- 3 files changed, 32 insertions(+), 20 deletions(-) diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index 02d9e79..eb00473 100644 --- a/target-ppc/excp_helper.c +++ b/target-ppc/excp_helper.c @@ -285,6 +285,10 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip); msr |= 0x00080000; env->spr[SPR_BOOKE_ESR] = ESR_PIL; + /* Some invalids will have the PC in the right place already */ + if (env->error_code & POWERPC_EXCP_INVAL_LSWX) { + goto store_next; + } break; case POWERPC_EXCP_PRIV: msr |= 0x00040000; @@ -306,6 +310,10 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) srr1 = SPR_HSRR1; new_msr |= (target_ulong)MSR_HVB; new_msr |= env->msr & ((target_ulong)1 << MSR_RI); + /* Some invalids will have the PC in the right place already */ + if (env->error_code == (POWERPC_EXCP_INVAL|POWERPC_EXCP_INVAL_LSWX)) { + goto store_next; + } goto store_current; case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ goto store_current; diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c index e4ed377..de96c91 100644 --- a/target-ppc/mem_helper.c +++ b/target-ppc/mem_helper.c @@ -77,23 +77,30 @@ void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg) } } -void helper_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb, uint32_t reg) +static void do_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb, + uint32_t reg, uintptr_t raddr) { int sh; for (; nb > 3; nb -= 4) { - env->gpr[reg] = cpu_ldl_data(env, addr); + env->gpr[reg] = cpu_ldl_data_ra(env, addr, raddr); reg = (reg + 1) % 32; addr = addr_add(env, addr, 4); } if (unlikely(nb > 0)) { env->gpr[reg] = 0; for (sh = 24; nb > 0; nb--, sh -= 8) { - env->gpr[reg] |= cpu_ldub_data(env, addr) << sh; + env->gpr[reg] |= cpu_ldub_data_ra(env, addr, raddr) << sh; addr = addr_add(env, addr, 1); } } } + +void helper_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb, uint32_t reg) +{ + do_lsw(env, addr, nb, reg, GETPC()); +} + /* PPC32 specification says we must generate an exception if * rA is in the range of registers to be loaded. * In an other hand, IBM says this is valid, but rA won't be loaded. @@ -106,12 +113,11 @@ void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg, int num_used_regs = (xer_bc + 3) / 4; if (unlikely((ra != 0 && lsw_reg_in_range(reg, num_used_regs, ra)) || lsw_reg_in_range(reg, num_used_regs, rb))) { - env->nip += 4; /* Compensate the "nip - 4" from gen_lswx() */ - helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM, - POWERPC_EXCP_INVAL | - POWERPC_EXCP_INVAL_LSWX); + raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, + POWERPC_EXCP_INVAL | + POWERPC_EXCP_INVAL_LSWX, GETPC()); } else { - helper_lsw(env, addr, xer_bc, reg); + do_lsw(env, addr, xer_bc, reg, GETPC()); } } } @@ -122,13 +128,13 @@ void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb, int sh; for (; nb > 3; nb -= 4) { - cpu_stl_data(env, addr, env->gpr[reg]); + cpu_stl_data_ra(env, addr, env->gpr[reg], GETPC()); reg = (reg + 1) % 32; addr = addr_add(env, addr, 4); } if (unlikely(nb > 0)) { for (sh = 24; nb > 0; nb--, sh -= 8) { - cpu_stb_data(env, addr, (env->gpr[reg] >> sh) & 0xFF); + cpu_stb_data_ra(env, addr, (env->gpr[reg] >> sh) & 0xFF, GETPC()); addr = addr_add(env, addr, 1); } } diff --git a/target-ppc/translate.c b/target-ppc/translate.c index a327072..568c1f8 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -2916,12 +2916,16 @@ static void gen_lswi(DisasContext *ctx) nb = 32; nr = (nb + 3) / 4; if (unlikely(lsw_reg_in_range(start, nr, ra))) { + /* The handler expects the PC to point to *this* instruction, + * so setting ctx->exception here prevents it from being + * improperly updated again by gen_inval_exception + */ + gen_update_nip(ctx, ctx->nip - 4); + ctx->exception = POWERPC_EXCP_HV_EMU; gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); return; } gen_set_access_type(ctx, ACCESS_INT); - /* NIP cannot be restored if the memory exception comes from an helper */ - gen_update_nip(ctx, ctx->nip - 4); t0 = tcg_temp_new(); gen_addr_register(ctx, t0); t1 = tcg_const_i32(nb); @@ -2938,8 +2942,6 @@ static void gen_lswx(DisasContext *ctx) TCGv t0; TCGv_i32 t1, t2, t3; gen_set_access_type(ctx, ACCESS_INT); - /* NIP cannot be restored if the memory exception comes from an helper */ - gen_update_nip(ctx, ctx->nip - 4); t0 = tcg_temp_new(); gen_addr_reg_index(ctx, t0); t1 = tcg_const_i32(rD(ctx->opcode)); @@ -2959,8 +2961,6 @@ static void gen_stswi(DisasContext *ctx) TCGv_i32 t1, t2; int nb = NB(ctx->opcode); gen_set_access_type(ctx, ACCESS_INT); - /* NIP cannot be restored if the memory exception comes from an helper */ - gen_update_nip(ctx, ctx->nip - 4); t0 = tcg_temp_new(); gen_addr_register(ctx, t0); if (nb == 0) @@ -2979,8 +2979,6 @@ static void gen_stswx(DisasContext *ctx) TCGv t0; TCGv_i32 t1, t2; gen_set_access_type(ctx, ACCESS_INT); - /* NIP cannot be restored if the memory exception comes from an helper */ - gen_update_nip(ctx, ctx->nip - 4); t0 = tcg_temp_new(); gen_addr_reg_index(ctx, t0); t1 = tcg_temp_new_i32(); @@ -4083,7 +4081,7 @@ static void gen_dcbz(DisasContext *ctx) static void gen_dst(DisasContext *ctx) { if (rA(ctx->opcode) == 0) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); } else { /* interpreted as no-op */ } @@ -4093,7 +4091,7 @@ static void gen_dst(DisasContext *ctx) static void gen_dstst(DisasContext *ctx) { if (rA(ctx->opcode) == 0) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); } else { /* interpreted as no-op */ }