From patchwork Tue Sep 6 03:42:45 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 9315639 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3E1DC60752 for ; Tue, 6 Sep 2016 05:09:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 30005288CF for ; Tue, 6 Sep 2016 05:09:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2051328B56; Tue, 6 Sep 2016 05:09:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7095F288CF for ; Tue, 6 Sep 2016 05:09:46 +0000 (UTC) Received: from localhost ([::1]:58635 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bh8dl-0003qh-AZ for patchwork-qemu-devel@patchwork.kernel.org; Tue, 06 Sep 2016 01:09:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50039) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bh7GO-0003AV-IM for qemu-devel@nongnu.org; Mon, 05 Sep 2016 23:41:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bh7GF-0007tE-Ca for qemu-devel@nongnu.org; Mon, 05 Sep 2016 23:41:31 -0400 Received: from ozlabs.org ([103.22.144.67]:39784) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bh7GE-0007lN-Nh; Mon, 05 Sep 2016 23:41:23 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 3sSspB0X7bz9t2B; Tue, 6 Sep 2016 13:41:17 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1473133282; bh=II0v85U8HVMpRRSz8l7fJB5QM2LTaKKA6N++/0OoVH4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=diKV7GMCBXGLY8Fcm9VPdWcU8JGnsZA7mDVuVhHR955tuhxemzZNtG7DMZ0IIrAnG maAY/t9a/9C9DKMVUEQYXrhepe/w0vVfuA+9H2WkbQfWMYJx2PJu+zXQTx80x6FoYX Y+rFnkuBOKqt1TnxJOO7+MCyb5ap5X8N89jz5c+E= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 6 Sep 2016 13:42:45 +1000 Message-Id: <1473133396-18940-36-git-send-email-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1473133396-18940-1-git-send-email-david@gibson.dropbear.id.au> References: <1473133396-18940-1-git-send-email-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PULL 35/66] ppc: Don't update NIP on conditional trap instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Gibson , qemu-ppc@nongnu.org, agraf@suse.de, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Benjamin Herrenschmidt This is no longer necessary as the helpers will properly retrieve the return address when needed. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/excp_helper.c | 6 ++++-- target-ppc/translate.c | 8 -------- 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index d31eece..882d529 100644 --- a/target-ppc/excp_helper.c +++ b/target-ppc/excp_helper.c @@ -1031,7 +1031,8 @@ void helper_tw(CPUPPCState *env, target_ulong arg1, target_ulong arg2, ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) || ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) || ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) { - raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); + raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, + POWERPC_EXCP_TRAP, GETPC()); } } @@ -1044,7 +1045,8 @@ void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2, ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) || ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) || ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01))))) { - raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); + raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, + POWERPC_EXCP_TRAP, GETPC()); } } #endif diff --git a/target-ppc/translate.c b/target-ppc/translate.c index f75cdc6..93cd98c 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -3580,8 +3580,6 @@ static void gen_sc(DisasContext *ctx) static void gen_tw(DisasContext *ctx) { TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); - /* Update the nip since this might generate a trap exception */ - gen_update_nip(ctx, ctx->nip - 4); gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); tcg_temp_free_i32(t0); @@ -3592,8 +3590,6 @@ static void gen_twi(DisasContext *ctx) { TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); - /* Update the nip since this might generate a trap exception */ - gen_update_nip(ctx, ctx->nip - 4); gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); tcg_temp_free(t0); tcg_temp_free_i32(t1); @@ -3604,8 +3600,6 @@ static void gen_twi(DisasContext *ctx) static void gen_td(DisasContext *ctx) { TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); - /* Update the nip since this might generate a trap exception */ - gen_update_nip(ctx, ctx->nip - 4); gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); tcg_temp_free_i32(t0); @@ -3616,8 +3610,6 @@ static void gen_tdi(DisasContext *ctx) { TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); - /* Update the nip since this might generate a trap exception */ - gen_update_nip(ctx, ctx->nip - 4); gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); tcg_temp_free(t0); tcg_temp_free_i32(t1);