From patchwork Tue Sep 6 03:42:48 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 9315755 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7CC1860760 for ; Tue, 6 Sep 2016 06:08:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 59BF728945 for ; Tue, 6 Sep 2016 06:08:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4C87328B2E; Tue, 6 Sep 2016 06:08:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A39ED28945 for ; Tue, 6 Sep 2016 06:08:25 +0000 (UTC) Received: from localhost ([::1]:59012 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bh9YW-0004Xo-DF for patchwork-qemu-devel@patchwork.kernel.org; Tue, 06 Sep 2016 02:08:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50129) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bh7GP-0003DB-Sp for qemu-devel@nongnu.org; Mon, 05 Sep 2016 23:41:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bh7GE-0007sw-Sl for qemu-devel@nongnu.org; Mon, 05 Sep 2016 23:41:33 -0400 Received: from ozlabs.org ([103.22.144.67]:55756) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bh7GE-0007l2-H6; Mon, 05 Sep 2016 23:41:22 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 3sSsp95zVPz9t23; Tue, 6 Sep 2016 13:41:18 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1473133281; bh=aJLdvtkldNcnvb7SVSWzBAau6NU4G+nwjAwaNQ31jHU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BqjtR4tQqCoN/okpRgil9YgoCyjFQGrOScjo24KCDJ5Ei9EalnEz2gzAWFAOyREuS xzA8QSlwTOS96lxWPa4s+LwQXuT/5iMteFbhkTE1B2cTnk+mGApt0CNQZ7EzK4rl9r 4Btbo0DmcXAJYz+qIFT6FG3zZEUCbHmexE0ngTGE= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 6 Sep 2016 13:42:48 +1000 Message-Id: <1473133396-18940-39-git-send-email-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1473133396-18940-1-git-send-email-david@gibson.dropbear.id.au> References: <1473133396-18940-1-git-send-email-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PULL 38/66] ppc: Make alignment exceptions suck less X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Gibson , qemu-ppc@nongnu.org, agraf@suse.de, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Benjamin Herrenschmidt The current alignment exception generation tries to load the opcode to put in DSISR from a context where a cpu_ldl_code() is really not a good idea. It might fault and longjmp out and that's not something we want happening here. Instead, pass the releavant opcode bits via the error_code. There are a couple of cases of alignment interrupts that won't set anything, the ones coming from access to direct store segments, but that doesn't happen in practice, nobody used direct store segments and they are gone from newer chips. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/excp_helper.c | 9 +++++---- target-ppc/translate.c | 2 +- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index 882d529..04ed4da 100644 --- a/target-ppc/excp_helper.c +++ b/target-ppc/excp_helper.c @@ -260,11 +260,12 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) } break; case POWERPC_EXCP_ALIGN: /* Alignment exception */ - /* XXX: this is false */ /* Get rS/rD and rA from faulting opcode */ - /* Broken for LE mode */ - env->spr[SPR_DSISR] |= (cpu_ldl_code(env, env->nip) - & 0x03FF0000) >> 16; + /* Note: the opcode fields will not be set properly for a direct + * store load/store, but nobody cares as nobody actually uses + * direct store segments. + */ + env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; break; case POWERPC_EXCP_PROGRAM: /* Program exception */ switch (env->error_code & ~0xF) { diff --git a/target-ppc/translate.c b/target-ppc/translate.c index bebd1cc..6bb0ba9 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -2417,7 +2417,7 @@ static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) tcg_gen_andi_tl(t0, EA, mask); tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); - t2 = tcg_const_i32(0); + t2 = tcg_const_i32(ctx->opcode & 0x03FF0000); gen_update_nip(ctx, ctx->nip - 4); gen_helper_raise_exception_err(cpu_env, t1, t2); tcg_temp_free_i32(t1);