From patchwork Tue Sep 6 03:42:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 9315695 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B778C601C0 for ; Tue, 6 Sep 2016 05:38:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9F54C28732 for ; Tue, 6 Sep 2016 05:38:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 93E8F28B4A; Tue, 6 Sep 2016 05:38:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id EB2A628732 for ; Tue, 6 Sep 2016 05:38:11 +0000 (UTC) Received: from localhost ([::1]:58808 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bh95H-0003Ln-3w for patchwork-qemu-devel@patchwork.kernel.org; Tue, 06 Sep 2016 01:38:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50254) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bh7GS-0003Fx-Pb for qemu-devel@nongnu.org; Mon, 05 Sep 2016 23:41:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bh7GI-0007w4-NO for qemu-devel@nongnu.org; Mon, 05 Sep 2016 23:41:36 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:48250) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bh7GH-0007kr-Na; Mon, 05 Sep 2016 23:41:26 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 3sSspD53QPz9s4n; Tue, 6 Sep 2016 13:41:20 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1473133284; bh=60YFDp/rX79Y8sKM3yot0fOfW2Ob9t7B1/Juyc3tM5g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TxbJ+9i4wDMl5wM/09kM92c7bQ1znkC8kK16IwcpdQkzoKqmmr1VolBnhalepGX2X dp8yBfFt/cA4+mrnNGC3gXnB1bnz4K7entvcD7XsJi/QthDOJdTE5DKeLW5mIpIHJa 0q3if3vUdClvd78Zo5/JT8Jxg4DXYqv2L/IiY9FA= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 6 Sep 2016 13:42:58 +1000 Message-Id: <1473133396-18940-49-git-send-email-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1473133396-18940-1-git-send-email-david@gibson.dropbear.id.au> References: <1473133396-18940-1-git-send-email-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 48/66] target-ppc: add dtstsfi[q] instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sandipan Das , Nikunj A Dadhania , agraf@suse.de, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Sandipan Das DFP Test Significance Immediate [Quad] Signed-off-by: Sandipan Das Signed-off-by: Nikunj A Dadhania Reviewed-by: David Gibson Signed-off-by: David Gibson --- target-ppc/dfp_helper.c | 35 +++++++++++++++++++++++++++++++++++ target-ppc/helper.h | 2 ++ target-ppc/translate/dfp-impl.c | 20 ++++++++++++++++++++ target-ppc/translate/dfp-ops.c | 14 ++++++++++++++ 4 files changed, 71 insertions(+) diff --git a/target-ppc/dfp_helper.c b/target-ppc/dfp_helper.c index db0ede6..9164fe7 100644 --- a/target-ppc/dfp_helper.c +++ b/target-ppc/dfp_helper.c @@ -647,6 +647,41 @@ uint32_t helper_##op(CPUPPCState *env, uint64_t *a, uint64_t *b) \ DFP_HELPER_TSTSF(dtstsf, 64) DFP_HELPER_TSTSF(dtstsfq, 128) +#define DFP_HELPER_TSTSFI(op, size) \ +uint32_t helper_##op(CPUPPCState *env, uint32_t a, uint64_t *b) \ +{ \ + struct PPC_DFP dfp; \ + unsigned uim; \ + \ + dfp_prepare_decimal##size(&dfp, 0, b, env); \ + \ + uim = a & 0x3F; \ + \ + if (unlikely(decNumberIsSpecial(&dfp.b))) { \ + dfp.crbf = 1; \ + } else if (uim == 0) { \ + dfp.crbf = 4; \ + } else if (unlikely(decNumberIsZero(&dfp.b))) { \ + /* Zero has no sig digits */ \ + dfp.crbf = 4; \ + } else { \ + unsigned nsd = dfp.b.digits; \ + if (uim < nsd) { \ + dfp.crbf = 8; \ + } else if (uim > nsd) { \ + dfp.crbf = 4; \ + } else { \ + dfp.crbf = 2; \ + } \ + } \ + \ + dfp_set_FPCC_from_CRBF(&dfp); \ + return dfp.crbf; \ +} + +DFP_HELPER_TSTSFI(dtstsfi, 64) +DFP_HELPER_TSTSFI(dtstsfiq, 128) + static void QUA_PPs(struct PPC_DFP *dfp) { dfp_set_FPRF_from_FRT(dfp); diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 9e4bb7b..68fd19e 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -645,6 +645,8 @@ DEF_HELPER_3(dtstex, i32, env, fprp, fprp) DEF_HELPER_3(dtstexq, i32, env, fprp, fprp) DEF_HELPER_3(dtstsf, i32, env, fprp, fprp) DEF_HELPER_3(dtstsfq, i32, env, fprp, fprp) +DEF_HELPER_3(dtstsfi, i32, env, i32, fprp) +DEF_HELPER_3(dtstsfiq, i32, env, i32, fprp) DEF_HELPER_5(dquai, void, env, fprp, fprp, i32, i32) DEF_HELPER_5(dquaiq, void, env, fprp, fprp, i32, i32) DEF_HELPER_5(dqua, void, env, fprp, fprp, fprp, i32) diff --git a/target-ppc/translate/dfp-impl.c b/target-ppc/translate/dfp-impl.c index bf59951..178d304 100644 --- a/target-ppc/translate/dfp-impl.c +++ b/target-ppc/translate/dfp-impl.c @@ -45,6 +45,24 @@ static void gen_##name(DisasContext *ctx) \ tcg_temp_free_ptr(rb); \ } +#define GEN_DFP_BF_I_B(name) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_i32 uim; \ + TCGv_ptr rb; \ + if (unlikely(!ctx->fpu_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_FPU); \ + return; \ + } \ + gen_update_nip(ctx, ctx->nip - 4); \ + uim = tcg_const_i32(UIMM5(ctx->opcode)); \ + rb = gen_fprp_ptr(rB(ctx->opcode)); \ + gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ + cpu_env, uim, rb); \ + tcg_temp_free_i32(uim); \ + tcg_temp_free_ptr(rb); \ +} + #define GEN_DFP_BF_A_DCM(name) \ static void gen_##name(DisasContext *ctx) \ { \ @@ -172,6 +190,8 @@ GEN_DFP_BF_A_B(dtstex) GEN_DFP_BF_A_B(dtstexq) GEN_DFP_BF_A_B(dtstsf) GEN_DFP_BF_A_B(dtstsfq) +GEN_DFP_BF_I_B(dtstsfi) +GEN_DFP_BF_I_B(dtstsfiq) GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC) GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC) GEN_DFP_T_A_B_I32_Rc(dqua, RMC) diff --git a/target-ppc/translate/dfp-ops.c b/target-ppc/translate/dfp-ops.c index 7f27d0f..6ef38e5 100644 --- a/target-ppc/translate/dfp-ops.c +++ b/target-ppc/translate/dfp-ops.c @@ -1,6 +1,9 @@ #define _GEN_DFP_LONG(name, op1, op2, mask) \ GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP) +#define _GEN_DFP_LONG_300(name, op1, op2, mask) \ +GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_ISA300) + #define _GEN_DFP_LONGx2(name, op1, op2, mask) \ GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \ GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP) @@ -14,6 +17,9 @@ GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP) #define _GEN_DFP_QUAD(name, op1, op2, mask) \ GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP) +#define _GEN_DFP_QUAD_300(name, op1, op2, mask) \ +GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_ISA300) + #define _GEN_DFP_QUADx2(name, op1, op2, mask) \ GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \ GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP) @@ -48,12 +54,18 @@ _GEN_DFP_QUAD(name, op1, op2, 0x001F0800) #define GEN_DFP_BF_A_B(name, op1, op2) \ _GEN_DFP_LONG(name, op1, op2, 0x00000001) +#define GEN_DFP_BF_A_B_300(name, op1, op2) \ +_GEN_DFP_LONG_300(name, op1, op2, 0x00400001) + #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \ _GEN_DFP_QUAD(name, op1, op2, 0x00610801) #define GEN_DFP_BF_A_Bp(name, op1, op2) \ _GEN_DFP_QUAD(name, op1, op2, 0x00600801) +#define GEN_DFP_BF_A_Bp_300(name, op1, op2) \ +_GEN_DFP_QUAD_300(name, op1, op2, 0x00400001) + #define GEN_DFP_BF_A_DCM(name, op1, op2) \ _GEN_DFP_LONGx2(name, op1, op2, 0x00600001) @@ -119,6 +131,8 @@ GEN_DFP_BF_A_B(dtstex, 0x02, 0x05), GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05), GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15), GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15), +GEN_DFP_BF_A_B_300(dtstsfi, 0x03, 0x15), +GEN_DFP_BF_A_Bp_300(dtstsfiq, 0x03, 0x15), GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02), GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02), GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),