From patchwork Wed Sep 7 10:28:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 9318817 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 21595607D3 for ; Wed, 7 Sep 2016 10:29:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 25FC229207 for ; Wed, 7 Sep 2016 10:29:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1A59729209; Wed, 7 Sep 2016 10:29:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6DD1329207 for ; Wed, 7 Sep 2016 10:28:59 +0000 (UTC) Received: from localhost ([::1]:39349 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bha6E-0002cR-Ee for patchwork-qemu-devel@patchwork.kernel.org; Wed, 07 Sep 2016 06:28:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33200) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bha5Y-0002YQ-Lw for qemu-devel@nongnu.org; Wed, 07 Sep 2016 06:28:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bha5W-0004aN-9B for qemu-devel@nongnu.org; Wed, 07 Sep 2016 06:28:15 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:54693) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bha5V-0004ZV-Ay; Wed, 07 Sep 2016 06:28:14 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 3sTfn63kJFz9sBR; Wed, 7 Sep 2016 20:28:10 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1473244090; bh=G0ysbdqq1CQHnJFuOcEb9mLp9rDYUojDeC0iVbCcbGs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lRGrrQmIdeGPsFy/hbhsk6+exCzvNcKa2kkcbp5Q2G/ib7M6PkvMKldW/sqOVBLB7 k1Cg7sVrvhfQfy2+2QXeH/SqFb8k2r48mxot28/bbyhZYmTrgR+gakX59zq/fg08eE gOBd4/sl9PpV3owlQM0M9kxszsXWhgTjiSl9c3Mw= From: David Gibson To: peter.maydell@linaro.org Date: Wed, 7 Sep 2016 20:28:42 +1000 Message-Id: <1473244183-31510-4-git-send-email-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1473244183-31510-1-git-send-email-david@gibson.dropbear.id.au> References: <1473244183-31510-1-git-send-email-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 03/64] target-ppc: Introduce Power9 family X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, thuth@redhat.com, Nikunj A Dadhania , agraf@suse.de, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, "Aneesh Kumar K.V" , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: "Aneesh Kumar K.V" The patch adds CPU PVR definition for POWER9 and enables QEMU to launch guests/linux-user in TCG mode. Signed-off-by: Aneesh Kumar K.V [ Added POWER9 alias, POWER9 SPAPR core and dropped MMU defines ] Signed-off-by: Nikunj A Dadhania [dwg: Dropped sPAPR core type again for now] Signed-off-by: David Gibson --- target-ppc/cpu-models.c | 5 +++ target-ppc/cpu-models.h | 1 + target-ppc/cpu-qom.h | 1 + target-ppc/mmu_helper.c | 2 +- target-ppc/translate_init.c | 86 ++++++++++++++++++++++++++++++++++++++++++++- 5 files changed, 93 insertions(+), 2 deletions(-) diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c index 5209e63..901cf40 100644 --- a/target-ppc/cpu-models.c +++ b/target-ppc/cpu-models.c @@ -1147,6 +1147,10 @@ "POWER8NVL v1.0") POWERPC_DEF("970_v2.2", CPU_POWERPC_970_v22, 970, "PowerPC 970 v2.2") + + POWERPC_DEF("POWER9_v1.0", CPU_POWERPC_POWER9_BASE, POWER9, + "POWER9 v1.0") + POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970, "PowerPC 970FX v1.0 (G5)") POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970, @@ -1395,6 +1399,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = { { "POWER8E", "POWER8E_v2.1" }, { "POWER8", "POWER8_v2.0" }, { "POWER8NVL", "POWER8NVL_v1.0" }, + { "POWER9", "POWER9_v1.0" }, { "970", "970_v2.2" }, { "970fx", "970fx_v3.1" }, { "970mp", "970mp_v1.1" }, diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h index f21a44c..7d9e6a2 100644 --- a/target-ppc/cpu-models.h +++ b/target-ppc/cpu-models.h @@ -562,6 +562,7 @@ enum { CPU_POWERPC_POWER8_v20 = 0x004D0200, CPU_POWERPC_POWER8NVL_BASE = 0x004C0000, CPU_POWERPC_POWER8NVL_v10 = 0x004C0100, + CPU_POWERPC_POWER9_BASE = 0x004E0000, CPU_POWERPC_970_v22 = 0x00390202, CPU_POWERPC_970FX_v10 = 0x00391100, CPU_POWERPC_970FX_v20 = 0x003C0200, diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h index 2864105..713deef 100644 --- a/target-ppc/cpu-qom.h +++ b/target-ppc/cpu-qom.h @@ -86,6 +86,7 @@ enum powerpc_mmu_t { POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | POWERPC_MMU_64K | POWERPC_MMU_AMR | 0x00000004, + /* FIXME Add POWERPC_MMU_3_OO defines */ /* Architecture 2.07 "degraded" (no 1T segments) */ POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR | 0x00000004, diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 3eb3cd7..737f338 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -1941,7 +1941,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) break; default: /* XXX: TODO */ - cpu_abort(CPU(cpu), "Unknown MMU model\n"); + cpu_abort(CPU(cpu), "Unknown MMU model %d\n", env->mmu_model); break; } } diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 7a9b15e..2d29ad8 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7459,7 +7459,8 @@ enum BOOK3S_CPU_TYPE { BOOK3S_CPU_POWER5PLUS, BOOK3S_CPU_POWER6, BOOK3S_CPU_POWER7, - BOOK3S_CPU_POWER8 + BOOK3S_CPU_POWER8, + BOOK3S_CPU_POWER9 }; static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, @@ -8241,6 +8242,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version) break; case BOOK3S_CPU_POWER7: case BOOK3S_CPU_POWER8: + case BOOK3S_CPU_POWER9: gen_spr_book3s_ids(env); gen_spr_amr(env, version >= BOOK3S_CPU_POWER8); gen_spr_book3s_purr(env); @@ -8293,6 +8295,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version) break; case BOOK3S_CPU_POWER7: case BOOK3S_CPU_POWER8: + case BOOK3S_CPU_POWER9: default: env->slb_nr = 32; break; @@ -8310,6 +8313,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version) ppcPOWER7_irq_init(ppc_env_get_cpu(env)); break; case BOOK3S_CPU_POWER8: + case BOOK3S_CPU_POWER9: init_excp_POWER8(env); ppcPOWER7_irq_init(ppc_env_get_cpu(env)); break; @@ -8772,6 +8776,86 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) pcc->l1_icache_size = 0x8000; pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; } +static void init_proc_POWER9(CPUPPCState *env) +{ + init_proc_book3s_64(env, BOOK3S_CPU_POWER9); +} + +static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) +{ + if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) { + return true; + } + return false; +} + +POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->fw_name = "PowerPC,POWER9"; + dc->desc = "POWER9"; + dc->props = powerpc_servercpu_properties; + pcc->pvr_match = ppc_pvr_match_power9; + pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; + pcc->init_proc = init_proc_POWER9; + pcc->check_pow = check_pow_nocheck; + pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | + PPC_FLOAT_FRSQRTES | + PPC_FLOAT_STFIWX | + PPC_FLOAT_EXT | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | + PPC_64B | PPC_64BX | PPC_ALTIVEC | + PPC_SEGMENT_64B | PPC_SLBI | + PPC_POPCNTB | PPC_POPCNTWD | + PPC_CILDST; + pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | + PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | + PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | + PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | + PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | + PPC2_TM | PPC2_PM_ISA206; + pcc->msr_mask = (1ull << MSR_SF) | + (1ull << MSR_TM) | + (1ull << MSR_VR) | + (1ull << MSR_VSX) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + /* Using 2.07 defines until new radix model is added. */ + pcc->mmu_model = POWERPC_MMU_2_07; +#if defined(CONFIG_SOFTMMU) + pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; + /* segment page size remain the same */ + pcc->sps = &POWER7_POWER8_sps; +#endif + pcc->excp_model = POWERPC_EXCP_POWER8; + pcc->bus_model = PPC_FLAGS_INPUT_POWER7; + pcc->bfd_mach = bfd_mach_ppc64; + pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | + POWERPC_FLAG_BE | POWERPC_FLAG_PMM | + POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | + POWERPC_FLAG_VSX | POWERPC_FLAG_TM; + pcc->l1_dcache_size = 0x8000; + pcc->l1_icache_size = 0x8000; + pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; +} #if !defined(CONFIG_USER_ONLY)