diff --git a/target-arc/Makefile.objs b/target-arc/Makefile.objs
index 6fdb000..cd3eebc 100644
--- a/target-arc/Makefile.objs
+++ b/target-arc/Makefile.objs
@@ -21,6 +21,7 @@
 obj-y   += translate.o
 obj-y   += helper.o
 obj-y   += cpu.o
+obj-y   += op_helper.o
 obj-y   += translate-inst.o
 obj-y   += gdbstub.o
 obj-y   += decode.o
diff --git a/target-arc/helper.h b/target-arc/helper.h
index 69c91fb..d480052 100644
--- a/target-arc/helper.h
+++ b/target-arc/helper.h
@@ -19,3 +19,6 @@
  */
 
 DEF_HELPER_1(debug, void, env)
+DEF_HELPER_2(norm, i32, env, i32)
+DEF_HELPER_2(normw, i32, env, i32)
+
diff --git a/target-arc/op_helper.c b/target-arc/op_helper.c
new file mode 100644
index 0000000..f372bbf
--- /dev/null
+++ b/target-arc/op_helper.c
@@ -0,0 +1,91 @@
+/*
+ * QEMU ARC CPU
+ *
+ * Copyright (c) 2016 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/helper-proto.h"
+#include "exec/ioport.h"
+
+#define AUX_ID_STATUS           0x000
+#define AUX_ID_SEMAPHORE        0x001
+#define AUX_ID_LP_START         0x002
+#define AUX_ID_LP_END           0x003
+#define AUX_ID_IDENTITY         0x004
+#define AUX_ID_DEBUG            0x005
+#define AUX_ID_PC               0x006
+
+#define AUX_ID_STATUS32         0x00A
+#define AUX_ID_STATUS32_L1      0x00B
+#define AUX_ID_STATUS32_L2      0x00C
+
+#define AUX_ID_MULHI            0x012
+
+#define AUX_ID_INT_VECTOR_BASE  0x025
+
+#define AUX_ID_INT_MACMODE      0x041
+
+#define AUX_ID_IRQ_LV12         0x043
+
+#define AUX_ID_IRQ_LEV          0x200
+#define AUX_ID_IRQ_HINT         0x201
+
+#define AUX_ID_ERET             0x400
+#define AUX_ID_ERBTA            0x401
+#define AUX_ID_ERSTATUS         0x402
+#define AUX_ID_ECR              0x403
+#define AUX_ID_EFA              0x404
+
+#define AUX_ID_ICAUSE1          0x40A
+#define AUX_ID_ICAUSE2          0x40B
+#define AUX_ID_IENABLE          0x40C
+#define AUX_ID_ITRIGGER         0x40D
+
+#define AUX_ID_BTA              0x412
+#define AUX_ID_BTA_L1           0x413
+#define AUX_ID_BTA_L2           0x414
+#define AUX_ID_IRQ_PULSE_CANSEL 0x415
+#define AUX_ID_IRQ_PENDING      0x416
+
+target_ulong helper_norm(CPUARCState *env, uint32_t src1)
+{
+    if (src1 == 0x00000000 || src1 == 0xffffffff) {
+        return 31;
+    } else {
+        if ((src1 & 0x80000000) == 0x80000000) {
+            src1 = ~src1;
+        }
+        return clz32(src1) - 1;
+    }
+}
+
+target_ulong helper_normw(CPUARCState *env, uint32_t src1)
+{
+    src1 &= 0xffff;
+
+    if (src1 == 0x0000 || src1 == 0xffff) {
+        return 15;
+    } else {
+        if ((src1 & 0x8000) == 0x8000) {
+            src1 = ~src1 & 0xffff;
+        }
+        return clz32(src1) - 17;
+    }
+}
+
diff --git a/target-arc/translate-inst.c b/target-arc/translate-inst.c
index a0d601e..00785bf 100644
--- a/target-arc/translate-inst.c
+++ b/target-arc/translate-inst.c
@@ -1365,3 +1365,55 @@ int arc_gen_RRC(DisasCtxt *ctx, TCGv dest, TCGv src1)
     return  BS_NONE;
 }
 
+/*
+    NORMW
+*/
+int arc_gen_NORMW(DisasCtxt *ctx, TCGv dest, TCGv src1)
+{
+    TCGv rslt = dest;
+
+    if (TCGV_EQUAL(dest, src1)) {
+        rslt = tcg_temp_new_i32();
+    }
+
+    gen_helper_normw(rslt, cpu_env, src1);
+
+    if (ctx->opt.f) {
+        tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, src1, ctx->zero);
+        tcg_gen_shri_tl(cpu_Nf, src1, 31);
+    }
+
+    if (!TCGV_EQUAL(dest, rslt)) {
+        tcg_gen_mov_tl(dest, rslt);
+        tcg_temp_free_i32(rslt);
+    }
+
+    return BS_NONE;
+}
+
+/*
+    NORM
+*/
+int arc_gen_NORM(DisasCtxt *ctx, TCGv dest, TCGv src1)
+{
+    TCGv rslt = dest;
+
+    if (TCGV_EQUAL(dest, src1)) {
+        rslt = tcg_temp_new_i32();
+    }
+
+    gen_helper_norm(rslt, cpu_env, src1);
+
+    if (ctx->opt.f) {
+        tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, src1, ctx->zero);
+        tcg_gen_shri_tl(cpu_Nf, src1, 31);
+    }
+
+    if (!TCGV_EQUAL(dest, rslt)) {
+        tcg_gen_mov_tl(dest, rslt);
+        tcg_temp_free_i32(rslt);
+    }
+
+    return BS_NONE;
+}
+
diff --git a/target-arc/translate-inst.h b/target-arc/translate-inst.h
index 5e1c52d..811c914 100644
--- a/target-arc/translate-inst.h
+++ b/target-arc/translate-inst.h
@@ -86,3 +86,7 @@ int arc_gen_BXOR(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2);
 
 int arc_gen_RRC(DisasCtxt *c, TCGv dest, TCGv src1);
 int arc_gen_RLC(DisasCtxt *c, TCGv dest, TCGv src1);
+
+int arc_gen_NORMW(DisasCtxt *c, TCGv dest, TCGv src1);
+int arc_gen_NORM(DisasCtxt *c, TCGv dest, TCGv src1);
+
