diff mbox

[RFC,v1,04/29] target-arc: AND, OR, XOR, BIC, TST

Message ID 1473373930-31547-5-git-send-email-mrolnik@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Michael Rolnik Sept. 8, 2016, 10:31 p.m. UTC 
Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
---
 target-arc/translate-inst.c | 119 ++++++++++++++++++++++++++++++++++++++++++++
 target-arc/translate-inst.h |   6 +++
 2 files changed, 125 insertions(+)

Comments

Richard Henderson Sept. 20, 2016, 11:35 p.m. UTC | #1 
On 09/08/2016 03:31 PM, Michael Rolnik wrote:
> +int arc_gen_AND(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2)
> +{
> +    TCGv rslt = dest;
> +
> +    if (TCGV_EQUAL(dest, src1) || TCGV_EQUAL(dest, src2)) {
> +        rslt = tcg_temp_new_i32();
> +    }
> +
> +    tcg_gen_and_tl(rslt, src1, src2);
> +
> +    if (ctx->opt.f) {
> +        tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero);
> +        tcg_gen_shri_tl(cpu_Nf, rslt, 31);
> +    }
> +
> +    if (!TCGV_EQUAL(dest, rslt)) {
> +        tcg_gen_mov_tl(dest, rslt);
> +        tcg_temp_free_i32(rslt);
> +    }

There is no reason for this rslt temporary stuff.
Unlike with add & sub, src1 & src2 are not used after the operation, for any of 
the logical operations.


r~
diff mbox

Patch

diff --git a/target-arc/translate-inst.c b/target-arc/translate-inst.c
index 7389e5c..5192f41 100644
--- a/target-arc/translate-inst.c
+++ b/target-arc/translate-inst.c
@@ -333,3 +333,122 @@  int arc_gen_CMP(DisasCtxt *ctx, TCGv src1, TCGv src2)
 
     return  BS_NONE;
 }
+
+/*
+    TST
+*/
+int arc_gen_TST(DisasCtxt *ctx, TCGv src1, TCGv src2)
+{
+    TCGv temp = tcg_temp_new_i32();
+
+    ctx->opt.f = 1;
+    arc_gen_AND(ctx, temp, src1, src2);
+    tcg_temp_free_i32(temp);
+
+    return BS_NONE;
+}
+
+/*
+    AND
+*/
+int arc_gen_AND(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2)
+{
+    TCGv rslt = dest;
+
+    if (TCGV_EQUAL(dest, src1) || TCGV_EQUAL(dest, src2)) {
+        rslt = tcg_temp_new_i32();
+    }
+
+    tcg_gen_and_tl(rslt, src1, src2);
+
+    if (ctx->opt.f) {
+        tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero);
+        tcg_gen_shri_tl(cpu_Nf, rslt, 31);
+    }
+
+    if (!TCGV_EQUAL(dest, rslt)) {
+        tcg_gen_mov_tl(dest, rslt);
+        tcg_temp_free_i32(rslt);
+    }
+
+    return  BS_NONE;
+}
+
+/*
+    OR
+*/
+int arc_gen_OR(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2)
+{
+    TCGv rslt = dest;
+
+    if (TCGV_EQUAL(dest, src1) || TCGV_EQUAL(dest, src2)) {
+        rslt = tcg_temp_new_i32();
+    }
+
+    tcg_gen_or_tl(rslt, src1, src2);
+
+    if (ctx->opt.f) {
+        tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero);
+        tcg_gen_shri_tl(cpu_Nf, rslt, 31);
+    }
+
+    if (!TCGV_EQUAL(dest, rslt)) {
+        tcg_gen_mov_tl(dest, rslt);
+        tcg_temp_free_i32(rslt);
+    }
+
+    return  BS_NONE;
+}
+
+/*
+    BIC
+*/
+int arc_gen_BIC(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2)
+{
+    TCGv rslt = dest;
+
+    if (TCGV_EQUAL(dest, src1) || TCGV_EQUAL(dest, src2)) {
+        rslt = tcg_temp_new_i32();
+    }
+
+    tcg_gen_andc_tl(rslt, src1, src2);  /*  rslt = src1 & ~src2             */
+
+    if (ctx->opt.f) {
+        tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero);
+        tcg_gen_shri_tl(cpu_Nf, rslt, 31);
+    }
+
+    if (!TCGV_EQUAL(dest, rslt)) {
+        tcg_gen_mov_tl(dest, rslt);
+        tcg_temp_free_i32(rslt);
+    }
+
+    return  BS_NONE;
+}
+
+/*
+    XOR
+*/
+int arc_gen_XOR(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2)
+{
+    TCGv rslt = dest;
+
+    if (TCGV_EQUAL(dest, src1) || TCGV_EQUAL(dest, src2)) {
+        rslt = tcg_temp_new_i32();
+    }
+
+    tcg_gen_xor_tl(rslt, src1, src2);
+
+    if (ctx->opt.f) {
+        tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero);
+        tcg_gen_shri_tl(cpu_Nf, rslt, 31);
+    }
+
+    if (!TCGV_EQUAL(dest, rslt)) {
+        tcg_gen_mov_tl(dest, rslt);
+        tcg_temp_free_i32(rslt);
+    }
+
+    return  BS_NONE;
+}
+
diff --git a/target-arc/translate-inst.h b/target-arc/translate-inst.h
index 40ed8a0..40ce696 100644
--- a/target-arc/translate-inst.h
+++ b/target-arc/translate-inst.h
@@ -36,3 +36,9 @@  int arc_gen_SBC(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2);
 int arc_gen_RSUB(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2);
 int arc_gen_CMP(DisasCtxt *c, TCGv src1, TCGv src2);
 
+int arc_gen_AND(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2);
+int arc_gen_OR(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2);
+int arc_gen_BIC(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2);
+int arc_gen_XOR(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2);
+int arc_gen_TST(DisasCtxt *c, TCGv src1, TCGv src2);
+