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Thu, 08 Sep 2016 15:32:42 -0700 (PDT) Received: from a0999b0126e1.ant.amazon.com ([94.230.86.12]) by smtp.gmail.com with ESMTPSA id d8sm276298wmi.0.2016.09.08.15.32.40 (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 08 Sep 2016 15:32:41 -0700 (PDT) From: Michael Rolnik To: qemu-devel@nongnu.org Date: Fri, 9 Sep 2016 01:31:46 +0300 Message-Id: <1473373930-31547-6-git-send-email-mrolnik@gmail.com> X-Mailer: git-send-email 2.4.9 (Apple Git-60) In-Reply-To: <1473373930-31547-1-git-send-email-mrolnik@gmail.com> References: <1473373930-31547-1-git-send-email-mrolnik@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH RFC v1 05/29] target-arc: ASL(m), ASR(m), LSR(m), ROR(m) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Rolnik Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Michael Rolnik --- target-arc/translate-inst.c | 212 ++++++++++++++++++++++++++++++++++++++++++++ target-arc/translate-inst.h | 9 ++ 2 files changed, 221 insertions(+) diff --git a/target-arc/translate-inst.c b/target-arc/translate-inst.c index 5192f41..2032823 100644 --- a/target-arc/translate-inst.c +++ b/target-arc/translate-inst.c @@ -452,3 +452,215 @@ int arc_gen_XOR(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2) return BS_NONE; } +/* + ASL +*/ +int arc_gen_ASL(DisasCtxt *ctx, TCGv dest, TCGv src1) +{ + arc_gen_ADD(ctx, dest, src1, src1); + + return BS_NONE; +} + +/* + ASLm +*/ +int arc_gen_ASLm(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2) +{ + TCGv rslt = dest; + TCGv t0 = tcg_temp_new_i32(); + + if (TCGV_EQUAL(dest, src1) || TCGV_EQUAL(dest, src2)) { + rslt = tcg_temp_new_i32(); + } + + tcg_gen_andi_tl(t0, src2, 31); + tcg_gen_shl_tl(rslt, src1, t0); + + if (ctx->opt.f) { + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero); + tcg_gen_shri_tl(cpu_Nf, rslt, 31); + tcg_gen_rotl_tl(cpu_Cf, src1, t0); + tcg_gen_andi_tl(cpu_Cf, cpu_Cf, 1); + } + + if (!TCGV_EQUAL(dest, rslt)) { + tcg_gen_mov_tl(dest, rslt); + tcg_temp_free_i32(rslt); + } + tcg_temp_free_i32(t0); + + return BS_NONE; +} + +/* + ASR +*/ +int arc_gen_ASR(DisasCtxt *ctx, TCGv dest, TCGv src1) +{ + TCGv rslt = dest; + + if (TCGV_EQUAL(dest, src1)) { + rslt = tcg_temp_new_i32(); + } + + tcg_gen_sari_tl(rslt, src1, 1); + + if (ctx->opt.f) { + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero); + tcg_gen_shri_tl(cpu_Nf, rslt, 31); + tcg_gen_andi_tl(cpu_Cf, src1, 1); + } + + if (!TCGV_EQUAL(dest, rslt)) { + tcg_gen_mov_tl(dest, rslt); + tcg_temp_free_i32(rslt); + } + + return BS_NONE; +} + +/* + ASRm +*/ +int arc_gen_ASRm(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2) +{ + TCGv rslt = dest; + TCGv t0 = tcg_temp_new_i32(); + + if (TCGV_EQUAL(dest, src1) || TCGV_EQUAL(dest, src2)) { + rslt = tcg_temp_new_i32(); + } + + tcg_gen_andi_tl(t0, src2, 31); + tcg_gen_sar_tl(rslt, src1, t0); + + if (ctx->opt.f) { + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero); + tcg_gen_shri_tl(cpu_Nf, rslt, 31); + tcg_gen_rotr_tl(cpu_Cf, src1, src2); + tcg_gen_shri_tl(cpu_Cf, cpu_Cf, 31); + } + + if (!TCGV_EQUAL(dest, rslt)) { + tcg_gen_mov_tl(dest, rslt); + tcg_temp_free_i32(rslt); + } + tcg_temp_free_i32(t0); + + return BS_NONE; +} + +/* + LSR +*/ +int arc_gen_LSR(DisasCtxt *ctx, TCGv dest, TCGv src1) +{ + TCGv rslt = dest; + + if (TCGV_EQUAL(dest, src1)) { + rslt = tcg_temp_new_i32(); + } + + tcg_gen_shri_tl(rslt, src1, 1); + + if (ctx->opt.f) { + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero); + tcg_gen_movi_tl(cpu_Nf, 0); + tcg_gen_andi_tl(cpu_Cf, src1, 1); + } + + if (!TCGV_EQUAL(dest, rslt)) { + tcg_gen_mov_tl(dest, rslt); + tcg_temp_free_i32(rslt); + } + + return BS_NONE; +} + +/* + LSRm +*/ +int arc_gen_LSRm(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2) +{ + TCGv rslt = dest; + TCGv t0 = tcg_temp_new_i32(); + + if (TCGV_EQUAL(dest, src1) || TCGV_EQUAL(dest, src2)) { + rslt = tcg_temp_new_i32(); + } + + tcg_gen_andi_tl(t0, src2, 31); + tcg_gen_shr_tl(rslt, src1, t0); + + if (ctx->opt.f) { + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero); + tcg_gen_shri_tl(cpu_Nf, rslt, 31); + tcg_gen_rotr_tl(cpu_Cf, src1, t0); + tcg_gen_shri_tl(cpu_Cf, cpu_Cf, 31); + } + + if (!TCGV_EQUAL(dest, rslt)) { + tcg_gen_mov_tl(dest, rslt); + tcg_temp_free_i32(rslt); + } + tcg_temp_free_i32(t0); + + return BS_NONE; +} + +/* + ROR +*/ +int arc_gen_ROR(DisasCtxt *ctx, TCGv dest, TCGv src1) +{ + TCGv rslt = dest; + + if (TCGV_EQUAL(dest, src1)) { + rslt = tcg_temp_new_i32(); + } + + tcg_gen_rotri_tl(rslt, src1, 1); + + if (ctx->opt.f) { + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero); + tcg_gen_shri_tl(cpu_Nf, rslt, 31); + tcg_gen_mov_tl(cpu_Cf, cpu_Nf); + } + + if (!TCGV_EQUAL(dest, rslt)) { + tcg_gen_mov_tl(dest, rslt); + tcg_temp_free_i32(rslt); + } + + return BS_NONE; +} + +/* + RORm +*/ +int arc_gen_RORm(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2) +{ + TCGv rslt = dest; + + if (TCGV_EQUAL(dest, src1)) { + rslt = tcg_temp_new_i32(); + } + + tcg_gen_andi_tl(rslt, src2, 0x1f); + tcg_gen_rotr_tl(rslt, src1, rslt); + + if (ctx->opt.f) { + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero); + tcg_gen_shri_tl(cpu_Nf, rslt, 31); + tcg_gen_mov_tl(cpu_Cf, cpu_Nf); + } + + if (!TCGV_EQUAL(dest, rslt)) { + tcg_gen_mov_tl(dest, rslt); + tcg_temp_free_i32(rslt); + } + + return BS_NONE; +} + diff --git a/target-arc/translate-inst.h b/target-arc/translate-inst.h index 40ce696..325f708 100644 --- a/target-arc/translate-inst.h +++ b/target-arc/translate-inst.h @@ -42,3 +42,12 @@ int arc_gen_BIC(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2); int arc_gen_XOR(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2); int arc_gen_TST(DisasCtxt *c, TCGv src1, TCGv src2); +int arc_gen_ASL(DisasCtxt *c, TCGv dest, TCGv src1); +int arc_gen_ASLm(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2); +int arc_gen_ASR(DisasCtxt *c, TCGv dest, TCGv src1); +int arc_gen_ASRm(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2); +int arc_gen_LSR(DisasCtxt *c, TCGv dest, TCGv src1); +int arc_gen_LSRm(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2); +int arc_gen_ROR(DisasCtxt *c, TCGv dest, TCGv src1); +int arc_gen_RORm(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2); +