From patchwork Fri Sep 9 04:23:38 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nikunj A. Dadhania" X-Patchwork-Id: 9322383 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1921B607D3 for ; Fri, 9 Sep 2016 04:24:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0ECAC29B82 for ; Fri, 9 Sep 2016 04:24:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0366529B84; Fri, 9 Sep 2016 04:24:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 95F9429B82 for ; Fri, 9 Sep 2016 04:24:27 +0000 (UTC) Received: from localhost ([::1]:55778 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1biDMX-0004JR-Ed for patchwork-qemu-devel@patchwork.kernel.org; Fri, 09 Sep 2016 00:24:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40369) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1biDMA-0004JJ-QJ for qemu-devel@nongnu.org; Fri, 09 Sep 2016 00:24:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1biDM4-0000wo-OU for qemu-devel@nongnu.org; Fri, 09 Sep 2016 00:24:00 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:54347 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1biDM4-0000wj-JS for qemu-devel@nongnu.org; Fri, 09 Sep 2016 00:23:56 -0400 Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id u894Neu9032626 for ; Fri, 9 Sep 2016 00:23:55 -0400 Received: from e23smtp08.au.ibm.com (e23smtp08.au.ibm.com [202.81.31.141]) by mx0b-001b2d01.pphosted.com with ESMTP id 25bc2rnmfe-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Fri, 09 Sep 2016 00:23:55 -0400 Received: from localhost by e23smtp08.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 9 Sep 2016 14:23:52 +1000 Received: from d23dlp03.au.ibm.com (202.81.31.214) by e23smtp08.au.ibm.com (202.81.31.205) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Fri, 9 Sep 2016 14:23:49 +1000 X-IBM-Helo: d23dlp03.au.ibm.com X-IBM-MailFrom: nikunj@linux.vnet.ibm.com X-IBM-RcptTo: qemu-devel@nongnu.org;qemu-ppc@nongnu.org Received: from d23relay08.au.ibm.com (d23relay08.au.ibm.com [9.185.71.33]) by d23dlp03.au.ibm.com (Postfix) with ESMTP id 922C03578052; Fri, 9 Sep 2016 14:23:48 +1000 (EST) Received: from d23av05.au.ibm.com (d23av05.au.ibm.com [9.190.234.119]) by d23relay08.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id u894NmmE58327098; Fri, 9 Sep 2016 14:23:48 +1000 Received: from d23av05.au.ibm.com (localhost [127.0.0.1]) by d23av05.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id u894Nlhx012456; Fri, 9 Sep 2016 14:23:48 +1000 Received: from abhimanyu.in.ibm.com ([9.79.248.225]) by d23av05.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id u894NiXs012393; Fri, 9 Sep 2016 14:23:45 +1000 From: Nikunj A Dadhania To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, benh@kernel.crashing.org Date: Fri, 9 Sep 2016 09:53:38 +0530 X-Mailer: git-send-email 2.7.4 X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16090904-0048-0000-0000-000001B7258B X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 16090904-0049-0000-0000-0000468201C5 Message-Id: <1473395018-15288-1-git-send-email-nikunj@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2016-09-09_01:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1609020000 definitions=main-1609090070 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH RFC] target-ppc: tlbie should have global effect X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com, rth@twiddle.net Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP tlbie (and H_REMOVE for pseries) should have a global effect. This is achieved by iterating and setting tlb_need_flush in all the CPUs. Suggested-by: Benjamin Herrenschmidt Signed-off-by: Nikunj A Dadhania --- Note: Haven't changed following POWERPC_MMU_32B and POWERPC_MMU_601 yet. As I am not sure about it. --- target-ppc/cpu.h | 3 ++- target-ppc/helper.h | 1 + target-ppc/helper_regs.h | 13 +++++++++---- target-ppc/mmu-hash64.c | 16 ++++++++++------ target-ppc/mmu_helper.c | 29 +++++++++++++++++++++++------ target-ppc/translate.c | 2 +- 6 files changed, 46 insertions(+), 18 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 1e808c8..59889f8 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1251,7 +1251,8 @@ void store_40x_sler (CPUPPCState *env, uint32_t val); void store_booke_tcr (CPUPPCState *env, target_ulong val); void store_booke_tsr (CPUPPCState *env, target_ulong val); void ppc_tlb_invalidate_all (CPUPPCState *env); -void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr); +void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr, + unsigned int global); void cpu_ppc_set_papr(PowerPCCPU *cpu); #endif #endif diff --git a/target-ppc/helper.h b/target-ppc/helper.h index dcf3f95..79fb688 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -561,6 +561,7 @@ DEF_HELPER_2(74xx_tlbd, void, env, tl) DEF_HELPER_2(74xx_tlbi, void, env, tl) DEF_HELPER_FLAGS_1(tlbia, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_2(tlbie, TCG_CALL_NO_RWG, void, env, tl) +DEF_HELPER_FLAGS_2(tlbiel, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(tlbiva, TCG_CALL_NO_RWG, void, env, tl) #if defined(TARGET_PPC64) DEF_HELPER_FLAGS_3(store_slb, TCG_CALL_NO_RWG, void, env, tl, tl) diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h index 3d279f1..f3eb21d 100644 --- a/target-ppc/helper_regs.h +++ b/target-ppc/helper_regs.h @@ -156,10 +156,15 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value, #if !defined(CONFIG_USER_ONLY) static inline void check_tlb_flush(CPUPPCState *env) { - CPUState *cs = CPU(ppc_env_get_cpu(env)); - if (env->tlb_need_flush) { - env->tlb_need_flush = 0; - tlb_flush(cs, 1); + CPUState *cs; + + CPU_FOREACH(cs) { + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + if (env->tlb_need_flush) { + env->tlb_need_flush = 0; + tlb_flush(cs, 1); + } } } #else diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index 8118143..a76c92b 100644 --- a/target-ppc/mmu-hash64.c +++ b/target-ppc/mmu-hash64.c @@ -907,12 +907,16 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong pte_index, target_ulong pte0, target_ulong pte1) { - /* - * XXX: given the fact that there are too many segments to - * invalidate, and we still don't have a tlb_flush_mask(env, n, - * mask) in QEMU, we just invalidate all TLBs - */ - tlb_flush(CPU(cpu), 1); + CPUState *cs; + + CPU_FOREACH(cs) { + /* + * XXX: given the fact that there are too many segments to + * invalidate, and we still don't have a tlb_flush_mask(env, n, + * mask) in QEMU, we just invalidate all TLBs + */ + tlb_flush(cs, 1); + } } void ppc_hash64_update_rmls(CPUPPCState *env) diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 696bb03..1923f1b 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -1946,7 +1946,8 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) } } -void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) +void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr, + unsigned int global) { #if !defined(FLUSH_ALL_TLBS) addr &= TARGET_PAGE_MASK; @@ -1979,7 +1980,14 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) * and we still don't have a tlb_flush_mask(env, n, mask) in QEMU, * we just invalidate all TLBs */ - env->tlb_need_flush = 1; + if (!global) { + env->tlb_need_flush = 1; + } else { + CPUState *other_cs; + CPU_FOREACH(other_cs) { + env->tlb_need_flush = 1; + } + } break; #endif /* defined(TARGET_PPC64) */ default: @@ -2078,7 +2086,12 @@ void helper_tlbia(CPUPPCState *env) void helper_tlbie(CPUPPCState *env, target_ulong addr) { - ppc_tlb_invalidate_one(env, addr); + ppc_tlb_invalidate_one(env, addr, 1); +} + +void helper_tlbiel(CPUPPCState *env, target_ulong addr) +{ + ppc_tlb_invalidate_one(env, addr, 0); } void helper_tlbiva(CPUPPCState *env, target_ulong addr) @@ -2757,7 +2770,7 @@ static inline void booke206_invalidate_ea_tlb(CPUPPCState *env, int tlbn, void helper_booke206_tlbivax(CPUPPCState *env, target_ulong address) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); + CPUState *cs; if (address & 0x4) { /* flush all entries */ @@ -2774,11 +2787,15 @@ void helper_booke206_tlbivax(CPUPPCState *env, target_ulong address) if (address & 0x8) { /* flush TLB1 entries */ booke206_invalidate_ea_tlb(env, 1, address); - tlb_flush(CPU(cpu), 1); + CPU_FOREACH(cs) { + tlb_flush(cs, 1); + } } else { /* flush TLB0 entries */ booke206_invalidate_ea_tlb(env, 0, address); - tlb_flush_page(CPU(cpu), address & MAS2_EPN_MASK); + CPU_FOREACH(cs) { + tlb_flush_page(cs, address & MAS2_EPN_MASK); + } } } diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 618334a..86a8fb6 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -4432,7 +4432,7 @@ static void gen_tlbiel(DisasContext *ctx) #else CHK_SV; - gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); + gen_helper_tlbiel(cpu_env, cpu_gpr[rB(ctx->opcode)]); #endif /* defined(CONFIG_USER_ONLY) */ }