diff mbox

[RFC,v1,17/22] target-i386: add cpuid Fn8000_001f

Message ID 147377817920.11859.9423132506504837623.stgit@brijesh-build-machine (mailing list archive)
State New, archived
Headers show

Commit Message

Brijesh Singh Sept. 13, 2016, 2:49 p.m. UTC
Fn8000_001f cpuid provides the memory encryption (aka C-bit)

Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
---
 target-i386/cpu.c |    3 +++
 1 file changed, 3 insertions(+)

Comments

Paolo Bonzini Sept. 13, 2016, 11:07 p.m. UTC | #1
On 13/09/2016 16:49, Brijesh Singh wrote:
> Fn8000_001f cpuid provides the memory encryption (aka C-bit)
> 
> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
> ---
>  target-i386/cpu.c |    3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index 6a1afab..e039c08 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -2625,6 +2625,9 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
>              *edx = 0;
>          }
>          break;
> +    case 0x8000001F:
> +        host_cpuid(index, 0, eax, ebx, ecx, edx);
> +        break;
>      case 0xC0000000:
>          *eax = env->cpuid_xlevel2;
>          *ebx = 0;
> 
> 
> 

This should only be visible to a SEV-enabled guest.  Also, the xlevel
should be bumped to 0x8000001F for SEV-enabled guests.

Paolo
Brijesh Singh Sept. 21, 2016, 4:20 p.m. UTC | #2
Hi Paolo,

On 09/13/2016 06:07 PM, Paolo Bonzini wrote:
>
>
> On 13/09/2016 16:49, Brijesh Singh wrote:
>> Fn8000_001f cpuid provides the memory encryption (aka C-bit)
>>
>> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
>> ---
>>  target-i386/cpu.c |    3 +++
>>  1 file changed, 3 insertions(+)
>>
>> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
>> index 6a1afab..e039c08 100644
>> --- a/target-i386/cpu.c
>> +++ b/target-i386/cpu.c
>> @@ -2625,6 +2625,9 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
>>              *edx = 0;
>>          }
>>          break;
>> +    case 0x8000001F:
>> +        host_cpuid(index, 0, eax, ebx, ecx, edx);
>> +        break;
>>      case 0xC0000000:
>>          *eax = env->cpuid_xlevel2;
>>          *ebx = 0;
>>
>>
>>
>
> This should only be visible to a SEV-enabled guest.  Also, the xlevel
> should be bumped to 0x8000001F for SEV-enabled guests.
>

Okay I will add sev_enabled() check before getting the cpuid.

Regarding xlevel, I am not able to locate qemu code which bumped the 
xelevel for KVM enabled guests. Maybe I am missing something, looking at 
code gave me impression that xlevel is obtained using CPUID_80000000. 
One of the KVM RFC patch [1] updates the min level. Do I need to do 
something more into qemu to bumped the xlevel?

http://marc.info/?l=linux-mm&m=147190934724195&w=2

> Paolo
>
Paolo Bonzini Sept. 21, 2016, 4:24 p.m. UTC | #3
On 21/09/2016 18:20, Brijesh Singh wrote:
> Hi Paolo,
> 
> On 09/13/2016 06:07 PM, Paolo Bonzini wrote:
>>
>>
>> On 13/09/2016 16:49, Brijesh Singh wrote:
>>> Fn8000_001f cpuid provides the memory encryption (aka C-bit)
>>>
>>> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
>>> ---
>>>  target-i386/cpu.c |    3 +++
>>>  1 file changed, 3 insertions(+)
>>>
>>> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
>>> index 6a1afab..e039c08 100644
>>> --- a/target-i386/cpu.c
>>> +++ b/target-i386/cpu.c
>>> @@ -2625,6 +2625,9 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t
>>> index, uint32_t count,
>>>              *edx = 0;
>>>          }
>>>          break;
>>> +    case 0x8000001F:
>>> +        host_cpuid(index, 0, eax, ebx, ecx, edx);
>>> +        break;
>>>      case 0xC0000000:
>>>          *eax = env->cpuid_xlevel2;
>>>          *ebx = 0;
>>>
>>>
>>>
>>
>> This should only be visible to a SEV-enabled guest.  Also, the xlevel
>> should be bumped to 0x8000001F for SEV-enabled guests.
>>
> 
> Okay I will add sev_enabled() check before getting the cpuid.
> 
> Regarding xlevel, I am not able to locate qemu code which bumped the
> xelevel for KVM enabled guests. Maybe I am missing something, looking at
> code gave me impression that xlevel is obtained using CPUID_80000000.
> One of the KVM RFC patch [1] updates the min level.

That patch makes sure that entry->eax is _at most_ 0x8000001f.  Here you
want to make sure that CPUID[0x80000000].EAX == 0x8000001f for SEV guests.

I think you need to change x86_cpu_load_def:

    object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);

if SEV is enabled, use max(0x8000001f, def->xlevel) instead of def->xlevel.

Paolo
 Do I need to do
> something more into qemu to bumped the xlevel?
> 
> http://marc.info/?l=linux-mm&m=147190934724195&w=2
> 
>> Paolo
>>
Eduardo Habkost Sept. 21, 2016, 6:21 p.m. UTC | #4
On Wed, Sep 21, 2016 at 11:20:59AM -0500, Brijesh Singh wrote:
> On 09/13/2016 06:07 PM, Paolo Bonzini wrote:
> > On 13/09/2016 16:49, Brijesh Singh wrote:
[...]
> > > +    case 0x8000001F:
> > > +        host_cpuid(index, 0, eax, ebx, ecx, edx);
> > > +        break;

Do we really need to expose the raw host CPUID values directly to
the guest? It will make it harder to support migration later.


> > >      case 0xC0000000:
> > >          *eax = env->cpuid_xlevel2;
> > >          *ebx = 0;
> > > 
> > > 
> > > 
> > 
> > This should only be visible to a SEV-enabled guest.  Also, the xlevel
> > should be bumped to 0x8000001F for SEV-enabled guests.
> > 
> 
> Okay I will add sev_enabled() check before getting the cpuid.
> 
> Regarding xlevel, I am not able to locate qemu code which bumped the xelevel
> for KVM enabled guests.

Because QEMU doesn't do that automatically (yet), except for
CPUID[7].EBX features.

> Maybe I am missing something, looking at code gave
> me impression that xlevel is obtained using CPUID_80000000. One of the KVM
> RFC patch [1] updates the min level. Do I need to do something more into
> qemu to bumped the xlevel?

I will send a series today that will increase level/xlevel
automatically depending on the features that are enabled. I will
add you to CC.
diff mbox

Patch

diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 6a1afab..e039c08 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2625,6 +2625,9 @@  void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
             *edx = 0;
         }
         break;
+    case 0x8000001F:
+        host_cpuid(index, 0, eax, ebx, ecx, edx);
+        break;
     case 0xC0000000:
         *eax = env->cpuid_xlevel2;
         *ebx = 0;