From patchwork Thu Sep 15 08:44:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 9332957 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8BCA16077A for ; Thu, 15 Sep 2016 08:45:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 778FF292BF for ; Thu, 15 Sep 2016 08:45:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 67B9E293F9; Thu, 15 Sep 2016 08:45:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 52A64292BF for ; Thu, 15 Sep 2016 08:45:48 +0000 (UTC) Received: from localhost ([::1]:32777 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bkSIl-0001N6-FZ for patchwork-qemu-devel@patchwork.kernel.org; Thu, 15 Sep 2016 04:45:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49835) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bkSIG-0001Ju-IQ for qemu-devel@nongnu.org; Thu, 15 Sep 2016 04:45:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bkSI8-0005Kh-VD for qemu-devel@nongnu.org; Thu, 15 Sep 2016 04:45:15 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:8071) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bkSI8-0005KK-MA for qemu-devel@nongnu.org; Thu, 15 Sep 2016 04:45:08 -0400 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Forcepoint Email with ESMTPS id 4D2E3D785CA1F; Thu, 15 Sep 2016 09:44:54 +0100 (IST) Received: from hhmipssw204.hh.imgtec.org (10.100.21.121) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.294.0; Thu, 15 Sep 2016 09:44:56 +0100 From: Leon Alrae To: Date: Thu, 15 Sep 2016 09:44:22 +0100 Message-ID: <1473929062-5548-3-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1473929062-5548-1-git-send-email-leon.alrae@imgtec.com> References: <1473929062-5548-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.21.121] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PATCH 2/2] target-mips: reimplement SC instruction and use cmpxchg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, rth@twiddle.net Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This patch completely rewrites conditional stores. Now we use cmpxchg and no longer need separate implementations for user and system emulation. Signed-off-by: Leon Alrae --- linux-user/main.c | 58 --------------------- target-mips/cpu.h | 4 -- target-mips/helper.c | 6 +-- target-mips/helper.h | 2 - target-mips/op_helper.c | 25 --------- target-mips/translate.c | 131 ++++++++++++++++++++++++------------------------ 6 files changed, 67 insertions(+), 159 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index 0d0bf9d..bc1b307 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -2230,55 +2230,6 @@ static const uint8_t mips_syscall_args[] = { # undef MIPS_SYS # endif /* O32 */ -static int do_store_exclusive(CPUMIPSState *env) -{ - target_ulong addr; - target_ulong page_addr; - target_ulong val; - int flags; - int segv = 0; - int reg; - int d; - - addr = env->lladdr; - page_addr = addr & TARGET_PAGE_MASK; - start_exclusive(); - mmap_lock(); - flags = page_get_flags(page_addr); - if ((flags & PAGE_READ) == 0) { - segv = 1; - } else { - reg = env->llreg & 0x1f; - d = (env->llreg & 0x20) != 0; - if (d) { - segv = get_user_s64(val, addr); - } else { - segv = get_user_s32(val, addr); - } - if (!segv) { - if (val != env->llval) { - env->active_tc.gpr[reg] = 0; - } else { - if (d) { - segv = put_user_u64(env->llnewval, addr); - } else { - segv = put_user_u32(env->llnewval, addr); - } - if (!segv) { - env->active_tc.gpr[reg] = 1; - } - } - } - } - env->lladdr = -1; - if (!segv) { - env->active_tc.PC += 4; - } - mmap_unlock(); - end_exclusive(); - return segv; -} - /* Break codes */ enum { BRK_OVERFLOW = 6, @@ -2426,15 +2377,6 @@ done_syscall: } } break; - case EXCP_SC: - if (do_store_exclusive(env)) { - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->active_tc.PC; - queue_signal(env, info.si_signo, &info); - } - break; case EXCP_DSPDIS: info.si_signo = TARGET_SIGILL; info.si_errno = 0; diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 78555b9..6c268f0 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -500,8 +500,6 @@ struct CPUMIPSState { /* XXX: Maybe make LLAddr per-TC? */ target_ulong lladdr; /* LL virtual address compared against SC */ target_ulong llval; - target_ulong llnewval; - target_ulong llreg; uint64_t CP0_LLAddr_rw_bitmask; int CP0_LLAddr_shift; target_ulong CP0_WatchLo[8]; @@ -796,8 +794,6 @@ enum { EXCP_LAST = EXCP_TLBRI, }; -/* Dummy exception for conditional stores. */ -#define EXCP_SC 0x100 /* * This is an interrnally generated WAKE request line. diff --git a/target-mips/helper.c b/target-mips/helper.c index c864b15..67b19e6 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -958,10 +958,8 @@ void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, { CPUState *cs = CPU(mips_env_get_cpu(env)); - if (exception < EXCP_SC) { - qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n", - __func__, exception, error_code); - } + qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n", + __func__, exception, error_code); cs->exception_index = exception; env->error_code = error_code; diff --git a/target-mips/helper.h b/target-mips/helper.h index 666936c..dd68751 100644 --- a/target-mips/helper.h +++ b/target-mips/helper.h @@ -13,10 +13,8 @@ DEF_HELPER_4(swr, void, env, tl, tl, int) #ifndef CONFIG_USER_ONLY DEF_HELPER_3(ll, tl, env, tl, int) -DEF_HELPER_4(sc, tl, env, tl, tl, int) #ifdef TARGET_MIPS64 DEF_HELPER_3(lld, tl, env, tl, int) -DEF_HELPER_4(scd, tl, env, tl, tl, int) #endif #endif diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index e0c9842..9f094ad 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -300,31 +300,6 @@ HELPER_LD_ATOMIC(ll, lw, 0x3) HELPER_LD_ATOMIC(lld, ld, 0x7) #endif #undef HELPER_LD_ATOMIC - -#define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \ -target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \ - target_ulong arg2, int mem_idx) \ -{ \ - target_long tmp; \ - \ - if (arg2 & almask) { \ - env->CP0_BadVAddr = arg2; \ - do_raise_exception(env, EXCP_AdES, GETPC()); \ - } \ - if (arg2 == env->lladdr) { \ - tmp = do_##ld_insn(env, arg2, mem_idx, GETPC()); \ - if (tmp == env->llval) { \ - do_##st_insn(env, arg2, arg1, mem_idx, GETPC()); \ - return 1; \ - } \ - } \ - return 0; \ -} -HELPER_ST_ATOMIC(sc, lw, sw, 0x3) -#ifdef TARGET_MIPS64 -HELPER_ST_ATOMIC(scd, ld, sd, 0x7) -#endif -#undef HELPER_ST_ATOMIC #endif #ifdef TARGET_WORDS_BIGENDIAN diff --git a/target-mips/translate.c b/target-mips/translate.c index 5d0732f..1936739 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1364,6 +1364,7 @@ static TCGv_i32 hflags; static TCGv_i32 fpu_fcr0, fpu_fcr31; static TCGv_i64 fpu_f64[32]; static TCGv_i64 msa_wr_d[64]; +static TCGv cpu_lladdr, cpu_llval; #include "exec/gen-icount.h" @@ -2050,46 +2051,6 @@ OP_LD_ATOMIC(lld,ld64); #endif #undef OP_LD_ATOMIC -#ifdef CONFIG_USER_ONLY -#define OP_ST_ATOMIC(insn,fname,ldname,almask) \ -static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \ -{ \ - TCGv t0 = tcg_temp_new(); \ - TCGLabel *l1 = gen_new_label(); \ - TCGLabel *l2 = gen_new_label(); \ - \ - tcg_gen_andi_tl(t0, arg2, almask); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); \ - tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr)); \ - generate_exception(ctx, EXCP_AdES); \ - gen_set_label(l1); \ - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); \ - tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \ - tcg_gen_movi_tl(t0, rt | ((almask << 3) & 0x20)); \ - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, llreg)); \ - tcg_gen_st_tl(arg1, cpu_env, offsetof(CPUMIPSState, llnewval)); \ - generate_exception_end(ctx, EXCP_SC); \ - gen_set_label(l2); \ - tcg_gen_movi_tl(t0, 0); \ - gen_store_gpr(t0, rt); \ - tcg_temp_free(t0); \ -} -#else -#define OP_ST_ATOMIC(insn,fname,ldname,almask) \ -static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \ -{ \ - TCGv t0 = tcg_temp_new(); \ - gen_helper_1e2i(insn, t0, arg1, arg2, ctx->mem_idx); \ - gen_store_gpr(t0, rt); \ - tcg_temp_free(t0); \ -} -#endif -OP_ST_ATOMIC(sc,st32,ld32s,0x3); -#if defined(TARGET_MIPS64) -OP_ST_ATOMIC(scd,st64,ld64,0x7); -#endif -#undef OP_ST_ATOMIC - static void gen_base_offset_addr (DisasContext *ctx, TCGv addr, int base, int16_t offset) { @@ -2335,33 +2296,66 @@ static void gen_st (DisasContext *ctx, uint32_t opc, int rt, /* Store conditional */ -static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt, - int base, int16_t offset) +static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset, + int size) { - TCGv t0, t1; + TCGv addr, t0, val; + TCGLabel *l1 = gen_new_label(); + TCGLabel *l2 = gen_new_label(); + TCGLabel *done = gen_new_label(); -#ifdef CONFIG_USER_ONLY t0 = tcg_temp_local_new(); - t1 = tcg_temp_local_new(); -#else - t0 = tcg_temp_new(); - t1 = tcg_temp_new(); -#endif - gen_base_offset_addr(ctx, t0, base, offset); - gen_load_gpr(t1, rt); - switch (opc) { -#if defined(TARGET_MIPS64) - case OPC_SCD: - case R6_OPC_SCD: - op_st_scd(t1, t0, rt, ctx); + addr = tcg_temp_local_new(); + /* check the alignment of the address */ + gen_base_offset_addr(ctx, addr, base, offset); + tcg_gen_andi_tl(t0, addr, size - 1); + tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); + tcg_gen_st_tl(addr, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr)); + generate_exception(ctx, EXCP_AdES); + tcg_gen_br(done); + + gen_set_label(l1); + /* compare the address against that of the preceeding LL */ + tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l2); + tcg_gen_movi_tl(t0, 0); + tcg_gen_br(done); + + gen_set_label(l2); + /* generate cmpxchg */ + val = tcg_temp_new(); + gen_load_gpr(val, rt); + switch (size) { +#ifdef TARGET_MIPS64 + case 8: /* SCD */ + tcg_gen_atomic_cmpxchg_i64(t0, addr, cpu_llval, val, + ctx->mem_idx, MO_TEQ); break; #endif - case OPC_SC: - case R6_OPC_SC: - op_st_sc(t1, t0, rt, ctx); + case 4: /* SC */ + { + TCGv_i32 val32 = tcg_temp_new_i32(); + TCGv_i32 llval32 = tcg_temp_new_i32(); + TCGv_i32 old32 = tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(val32, val); + tcg_gen_trunc_tl_i32(llval32, cpu_llval); + + tcg_gen_atomic_cmpxchg_i32(old32, addr, llval32, val32, + ctx->mem_idx, MO_TESL); + tcg_gen_ext_i32_tl(t0, old32); + + tcg_temp_free_i32(old32); + tcg_temp_free_i32(llval32); + tcg_temp_free_i32(val32); + } break; } - tcg_temp_free(t1); + tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_llval); + tcg_temp_free(val); + + gen_set_label(done); + /* store the result into the register */ + gen_store_gpr(t0, rt); + tcg_temp_free(addr); tcg_temp_free(t0); } @@ -14700,13 +14694,13 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) gen_st(ctx, mips32_op, rt, rs, SIMM(ctx->opcode, 0, 12)); break; case SC: - gen_st_cond(ctx, OPC_SC, rt, rs, offset); + gen_st_cond(ctx, rt, rs, offset, 4); break; #if defined(TARGET_MIPS64) case SCD: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - gen_st_cond(ctx, OPC_SCD, rt, rs, offset); + gen_st_cond(ctx, rt, rs, offset, 8); break; #endif case PREF: @@ -17421,7 +17415,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx) } break; case R6_OPC_SC: - gen_st_cond(ctx, op1, rt, rs, imm); + gen_st_cond(ctx, rt, rs, imm, 4); break; case R6_OPC_LL: gen_ld(ctx, op1, rt, rs, imm); @@ -17445,7 +17439,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx) break; #if defined(TARGET_MIPS64) case R6_OPC_SCD: - gen_st_cond(ctx, op1, rt, rs, imm); + gen_st_cond(ctx, rt, rs, imm, 8); break; case R6_OPC_LLD: gen_ld(ctx, op1, rt, rs, imm); @@ -19521,7 +19515,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) case OPC_SC: check_insn(ctx, ISA_MIPS2); check_insn_opc_removed(ctx, ISA_MIPS32R6); - gen_st_cond(ctx, op, rt, rs, imm); + gen_st_cond(ctx, rt, rs, imm, 4); break; case OPC_CACHE: check_insn_opc_removed(ctx, ISA_MIPS32R6); @@ -19807,7 +19801,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) check_insn_opc_removed(ctx, ISA_MIPS32R6); check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - gen_st_cond(ctx, op, rt, rs, imm); + gen_st_cond(ctx, rt, rs, imm, 8); break; case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */ if (ctx->insn_flags & ISA_MIPS32R6) { @@ -20180,6 +20174,11 @@ void mips_tcg_init(void) offsetof(CPUMIPSState, active_fpu.fcr31), "fcr31"); + cpu_lladdr = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, lladdr), + "lladdr"); + cpu_llval = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, llval), + "llval"); + inited = 1; }