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X-Mailer: git-send-email 2.1.4 In-Reply-To: <1474393246-29085-1-git-send-email-davidkiarie4@gmail.com> References: <1474393246-29085-1-git-send-email-davidkiarie4@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 74.125.82.66 Subject: [Qemu-devel] [V5 3/6] hw/iommu: Prepare for AMD IOMMU interrupt remapping X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Kiarie Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Introduce macros and trace events for use in AMD IOMMU interrupt remapping Signed-off-by: David Kiarie --- hw/i386/amd_iommu.h | 80 ++++++++++++++++++++++++++++++++++++++++++++++++++++ hw/i386/trace-events | 7 +++++ 2 files changed, 87 insertions(+) diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index 884926e..5c4a13b 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -177,6 +177,68 @@ #define AMDVI_IOTLB_MAX_SIZE 1024 #define AMDVI_DEVID_SHIFT 36 +/* interrupt types */ +#define AMDVI_MT_FIXED 0x0 +#define AMDVI_MT_ARBIT 0x1 +#define AMDVI_MT_SMI 0x2 +#define AMDVI_MT_NMI 0x3 +#define AMDVI_MT_INIT 0x4 +#define AMDVI_MT_EXTINT 0x6 +#define AMDVI_MT_LINT1 0xb +#define AMDVI_MT_LINT0 0xe + +/* MSI interrupt type mask */ +#define AMDVI_IR_TYPE_MASK 0x300 + +/* interrupt destination mode */ +#define AMDVI_IRDEST_MODE_MASK 0x2 + +/* select MSI data 10:0 bits */ +#define AMDVI_IRTE_INDEX_MASK 0x7ff + +/* bits determining whether specific interrupts should be passed + * split DTE into 64-bit chunks + */ +#define AMDVI_DTE_INTPASS_LSHIFT 56 +#define AMDVI_DTE_EINTPASS_LSHIFT 57 +#define AMDVI_DTE_NMIPASS_LSHIFT 58 +#define AMDVI_DTE_INTCTL_RSHIFT 60 +#define AMDVI_DTE_LINT0PASS_LSHIFT 62 +#define AMDVI_DTE_LINT1PASS_LSHIFT 63 + +/* INTCTL expected values */ +#define AMDVI_INTCTL_ABORT 0x0 +#define AMDVI_INTCTL_PASS 0x1 +#define AMDVI_INTCTL_REMAP 0x2 +#define AMDVI_INTCTL_RSVD 0x3 + +/* interrupt data valid */ +#define AMDVI_IR_VALID (1UL << 0) + +/* interrupt root table mask */ +#define AMDVI_IRTEROOT_MASK 0xffffffffffffc0 + +/* default IRTE size */ +#define AMDVI_DEFAULT_IRTE_SIZE 0x4 + +#define AMDVI_IR_TABLE_SIZE_MASK 0xfe + +/* offsets into MSI data */ +#define AMDVI_MSI_DATA_DM_RSHIFT 0x8 +#define AMDVI_MSI_DATA_LEVEL_RSHIFT 0xe +#define AMDVI_MSI_DATA_TRM_RSHIFT 0xf + +/* offsets into MSI address */ +#define AMDVI_MSI_ADDR_DM_RSHIFT 0x2 +#define AMDVI_MSI_ADDR_RH_RSHIFT 0x3 +#define AMDVI_MSI_ADDR_DEST_RSHIFT 0xc + +#define AMDVI_BUS_NUM 0x0 +/* AMD-Vi specific IOAPIC Device function */ +#define AMDVI_DEVFN_IOAPIC 0xa0 + +#define AMDVI_LOCAL_APIC_ADDR 0xfee00000 + /* extended feature support */ #define AMDVI_EXT_FEATURES (AMDVI_FEATURE_PREFETCH | AMDVI_FEATURE_PPR | \ AMDVI_FEATURE_IA | AMDVI_FEATURE_GT | AMDVI_FEATURE_HE | \ @@ -214,6 +276,24 @@ #define AMDVI_INT_ADDR_FIRST 0xfee00000 #define AMDVI_INT_ADDR_LAST 0xfeefffff +#define AMDVI_INT_ADDR_SIZE ((AMDVI_INT_ADDR_LAST - \ + AMDVI_INT_ADDR_FIRST) + 1) +/* AMD IOMMU errors */ +#define AMDVI_ILLEG_DEV_TAB 0x1 +#define AMDVI_IOPF_ 0x2 +#define AMDVI_DEV_TAB_HW 0x3 +#define AMDVI_PAGE_TAB_HW 0x4 +#define AMDVI_ILLEG_COM 0x5 +#define AMDVI_COM_HW 0x6 +#define AMDVI_IOTLB_TIMEOUT 0x7 +#define AMDVI_INVAL_DEV_REQ 0x8 +#define AMDVI_INVAL_PPR_REQ 0x9 +#define AMDVI_EVT_COUNT_ZERO 0xa + +/* represent target and master aborts error state */ +#define AMDVI_TARGET_ABORT 0xb +#define AMDVI_MASTER_ABORT 0xc + #define TYPE_AMD_IOMMU_DEVICE "amd-iommu" #define AMD_IOMMU_DEVICE(obj)\ OBJECT_CHECK(AMDVIState, (obj), TYPE_AMD_IOMMU_DEVICE) diff --git a/hw/i386/trace-events b/hw/i386/trace-events index 1938b98..58c5bf7 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -42,3 +42,10 @@ amdvi_mode_invalid(uint8_t level, uint64_t addr)"error: translation level 0x%"PR amdvi_page_fault(uint64_t addr) "error: page fault accessing guest physical address 0x%"PRIx64 amdvi_iotlb_hit(uint8_t bus, uint8_t slot, uint8_t func, uint64_t addr, uint64_t txaddr) "hit iotlb devid %02x:%02x.%x gpa 0x%"PRIx64" hpa 0x%"PRIx64 amdvi_translation_result(uint8_t bus, uint8_t slot, uint8_t func, uint64_t addr, uint64_t txaddr) "devid: %02x:%02x.%x gpa 0x%"PRIx64" hpa 0x%"PRIx64 +amdvi_irte_get_fail(uint64_t addr, uint64_t offset) "couldn't access device table entry 0x%"PRIx64" + offset 0x%"PRIx64 +amdvi_invalid_irte_entry(uint8_t devid, uint64_t offset) "devid 0x%"PRIx8" requested IRTE offset 0x%"PRIx64" outside IR table range" +amdvi_ir_request(uint32_t data, uint64_t addr, uint16_t sid) "IR request data 0x%"PRIx32" address 0x%"PRIx64" SID 0x%"PRIx16 +amdvi_ir_remap(uint32_t data, uint64_t addr, uint16_t sid) "IR remap data 0x%"PRIx32" address 0x%"PRIx64" SID 0x%"PRIx16 +amdvi_ir_target_abort(uint32_t data, uint64_t addr, uint16_t sid) "IR target abort data 0x%"PRIx32" address 0x%"PRIx64" SID 0x%"PRIx16 +amdvi_ir_write_fail(uint64_t addr, uint32_t data) "fail to write to addr 0x%"PRIx64" value 0x%"PRIx32 +amdvi_ir_read_fail(uint64_t addr) " fail to read from addr 0x%"PRIx64