@@ -20,6 +20,7 @@
* Cache implementation inspired by hw/i386/intel_iommu.c
*/
#include "qemu/osdep.h"
+#include "qemu/error-report.h"
#include "hw/i386/amd_iommu.h"
#include "trace.h"
@@ -458,6 +459,7 @@ static void amdvi_inval_inttable(AMDVIState *s, uint64_t *cmd)
return;
}
+ x86_iommu_iec_notify_all(X86_IOMMU_DEVICE(s), true, 0, 0);
trace_amdvi_intr_inval();
}
@@ -1021,6 +1023,193 @@ static IOMMUTLBEntry amdvi_translate(MemoryRegion *iommu, hwaddr addr,
return ret;
}
+static inline int amdvi_ir_handle_non_vectored(MSIMessage *src,
+ MSIMessage *dst, uint8_t bitpos,
+ uint64_t dte)
+{
+ if ((dte & (1UL << bitpos))) {
+ /* passing interrupt enabled */
+ memcpy(dst, src, sizeof(*dst));
+ } else {
+ /* should be target aborted */
+ return -AMDVI_TARGET_ABORT;
+ }
+ return 0;
+}
+
+static int amdvi_remap_ir_intctl(uint64_t dte, uint32_t irte,
+ MSIMessage *src, MSIMessage *dst)
+{
+ int ret = 0;
+
+ switch ((dte >> AMDVI_DTE_INTCTL_RSHIFT) & 3UL) {
+ case AMDVI_INTCTL_PASS:
+ /* pass */
+ memcpy(dst, src, sizeof(*dst));
+ break;
+ case AMDVI_INTCTL_REMAP:
+ /* remap */
+ if (extract32(irte, 0, 1)) {
+ /* LOCAL APIC address */
+ dst->address = AMDVI_LOCAL_APIC_ADDR;
+ /* destination mode */
+ dst->address |= ((uint64_t)extract32(irte, 6, 1)) <<
+ AMDVI_MSI_ADDR_DM_RSHIFT;
+ /* RH */
+ dst->address |= ((uint64_t)extract32(irte, 5, 1)) <<
+ AMDVI_MSI_ADDR_RH_RSHIFT;
+ /* Destination ID */
+ dst->address |= ((uint64_t)extract32(irte, 8, 8)) <<
+ AMDVI_MSI_ADDR_DEST_RSHIFT;
+ /* construct data - vector */
+ dst->data |= extract32(irte, 16, 8);
+ /* Interrupt type */
+ dst->data |= ((uint64_t)extract32(irte, 2, 3)) <<
+ AMDVI_MSI_DATA_DM_RSHIFT;
+ } else {
+ ret = -AMDVI_TARGET_ABORT;
+ }
+ break;
+ case AMDVI_INTCTL_ABORT:
+ case AMDVI_INTCTL_RSVD:
+ ret = -AMDVI_TARGET_ABORT;
+ }
+ return ret;
+}
+
+static int amdvi_irte_get(AMDVIState *s, MSIMessage *src, uint32_t *irte,
+ uint64_t *dte, uint16_t devid)
+{
+ uint64_t irte_root, offset = devid * AMDVI_DEVTAB_ENTRY_SIZE,
+ ir_table_size;
+
+ irte_root = dte[2] & AMDVI_IRTEROOT_MASK;
+ offset = (src->data & AMDVI_IRTE_INDEX_MASK) << 2;
+ ir_table_size = 1UL << (dte[2] & AMDVI_IR_TABLE_SIZE_MASK);
+ /* enforce IR table size */
+ if (offset > (ir_table_size * AMDVI_DEFAULT_IRTE_SIZE)) {
+ trace_amdvi_invalid_irte_entry(offset, ir_table_size);
+ return -AMDVI_TARGET_ABORT;
+ }
+ /* read IRTE */
+ if (dma_memory_read(&address_space_memory, irte_root + offset,
+ irte, sizeof(*irte))) {
+ trace_amdvi_irte_get_fail(irte_root, offset);
+ return -AMDVI_DEV_TAB_HW;
+ }
+ return 0;
+}
+
+static int amdvi_int_remap(X86IOMMUState *iommu, MSIMessage *src,
+ MSIMessage *dst, uint16_t sid)
+{
+ trace_amdvi_ir_request(src->data, src->address, sid);
+
+ AMDVIState *s = AMD_IOMMU_DEVICE(iommu);
+ int ret = 0;
+ uint64_t dte[4];
+ uint32_t bitpos, irte;
+
+ amdvi_get_dte(s, sid, dte);
+
+ /* interrupt remapping disabled */
+ if (!(dte[2] & AMDVI_IR_VALID)) {
+ memcpy(dst, src, sizeof(*src));
+ return ret;
+ }
+
+ ret = amdvi_irte_get(s, src, &irte, dte, sid);
+ if (ret < 0) {
+ goto remap_fail;
+ }
+ switch (src->data & AMDVI_IR_TYPE_MASK) {
+ case AMDVI_MT_FIXED:
+ case AMDVI_MT_ARBIT:
+ ret = amdvi_remap_ir_intctl(dte[2], irte, src, dst);
+ if (ret < 0) {
+ goto remap_fail;
+ } else {
+ trace_amdvi_ir_remap(dst->data, dst->address, sid);
+ return ret;
+ }
+ /* not handling SMI currently */
+ case AMDVI_MT_SMI:
+ error_report("SMI interrupts not currently handled");
+ goto remap_fail;
+ case AMDVI_MT_NMI:
+ bitpos = AMDVI_DTE_NMIPASS_LSHIFT;
+ break;
+ case AMDVI_MT_INIT:
+ bitpos = AMDVI_DTE_INTPASS_LSHIFT;
+ break;
+ case AMDVI_MT_EXTINT:
+ bitpos = AMDVI_DTE_EINTPASS_LSHIFT;
+ break;
+ case AMDVI_MT_LINT1:
+ bitpos = AMDVI_DTE_LINT1PASS_LSHIFT;
+ break;
+ case AMDVI_MT_LINT0:
+ bitpos = AMDVI_DTE_LINT0PASS_LSHIFT;
+ default:
+ goto remap_fail;
+ }
+
+ ret = amdvi_ir_handle_non_vectored(src, dst, bitpos, dte[2]);
+ if (ret < 0) {
+ goto remap_fail;
+ }
+ trace_amdvi_ir_remap(dst->data, dst->address, sid);
+ return ret;
+remap_fail:
+ trace_amdvi_ir_target_abort(dst->data, dst->address, sid);
+ return ret;
+}
+
+static MemTxResult amdvi_ir_read(void *opaque, hwaddr addr,
+ uint64_t *data, unsigned size,
+ MemTxAttrs attrs)
+{
+ return MEMTX_OK;
+}
+
+static MemTxResult amdvi_ir_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size, MemTxAttrs attrs)
+{
+ AMDVIAddressSpace *as = opaque;
+ MSIMessage from = { addr + AMDVI_INT_ADDR_FIRST, val }, to = { 0, 0};
+ int ret = 0;
+
+ ret = amdvi_int_remap(X86_IOMMU_DEVICE(as->iommu_state), &from, &to,
+ attrs.requester_id);
+
+ if (ret < 0) {
+ trace_amdvi_ir_target_abort(from.data, from.address,
+ attrs.requester_id);
+ return MEMTX_ERROR;
+ }
+
+ if (dma_memory_write(&address_space_memory, to.address, &to.data, size)) {
+ trace_amdvi_ir_write_fail(to.address, to.data);
+ return MEMTX_ERROR;
+ }
+
+ return MEMTX_OK;
+}
+
+static const MemoryRegionOps amdvi_ir_ops = {
+ .read_with_attrs = amdvi_ir_read,
+ .write_with_attrs = amdvi_ir_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ }
+};
+
static AddressSpace *amdvi_host_dma_iommu(PCIBus *bus, void *opaque, int devfn)
{
AMDVIState *s = opaque;
@@ -1044,6 +1233,12 @@ static AddressSpace *amdvi_host_dma_iommu(PCIBus *bus, void *opaque, int devfn)
memory_region_init_iommu(&iommu_as[devfn]->iommu, OBJECT(s),
&s->iommu_ops, "amd-iommu", UINT64_MAX);
+ memory_region_init_io(&iommu_as[devfn]->iommu_ir, OBJECT(s),
+ &amdvi_ir_ops, iommu_as[devfn], "amd-iommu-ir",
+ AMDVI_INT_ADDR_SIZE);
+ memory_region_add_subregion(&iommu_as[devfn]->iommu,
+ AMDVI_INT_ADDR_FIRST,
+ &iommu_as[devfn]->iommu_ir);
address_space_init(&iommu_as[devfn]->as, &iommu_as[devfn]->iommu,
"amd-iommu");
}
@@ -1131,11 +1326,15 @@ static void amdvi_realize(DeviceState *dev, Error **err)
AMDVIState *s = AMD_IOMMU_DEVICE(dev);
X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(dev);
PCIBus *bus = PC_MACHINE(qdev_get_machine())->bus;
+ PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
s->iotlb = g_hash_table_new_full(amdvi_uint64_hash,
amdvi_uint64_equal, g_free, g_free);
- /* This device should take care of IOMMU PCI properties */
+ /* AMD IOMMU has Interrupt Remapping on by default */
+ x86_iommu->intr_supported = true;
x86_iommu->type = TYPE_AMD;
+
+ /* This device should take care of IOMMU PCI properties */
qdev_set_parent_bus(DEVICE(&s->pci), &bus->qbus);
object_property_set_bool(OBJECT(&s->pci), true, "realized", err);
s->capab_offset = pci_add_capability(&s->pci.dev, AMDVI_CAPAB_ID_SEC, 0,
@@ -1147,9 +1346,13 @@ static void amdvi_realize(DeviceState *dev, Error **err)
memory_region_init_io(&s->mmio, OBJECT(s), &mmio_mem_ops, s, "amdvi-mmio",
AMDVI_MMIO_SIZE);
+ x86_iommu->ioapic_bdf = PCI_BUILD_BDF(AMDVI_BUS_NUM,
+ AMDVI_SB_IOAPIC_ID);
+
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, AMDVI_BASE_ADDR);
pci_setup_iommu(bus, amdvi_host_dma_iommu, s);
+ pcms->ioapic_as = amdvi_host_dma_iommu(bus, s, AMDVI_SB_IOAPIC_ID);
s->devid = object_property_get_int(OBJECT(&s->pci), "addr", err);
msi_init(&s->pci.dev, 0, 1, true, false, err);
amdvi_init(s);
@@ -1176,6 +1379,7 @@ static void amdvi_class_init(ObjectClass *klass, void* data)
dc->vmsd = &vmstate_amdvi;
dc->hotpluggable = false;
dc_class->realize = amdvi_realize;
+ dc_class->int_remap = amdvi_int_remap;
}
static const TypeInfo amdvi = {
@@ -235,7 +235,7 @@
#define AMDVI_BUS_NUM 0x0
/* AMD-Vi specific IOAPIC Device function */
-#define AMDVI_DEVFN_IOAPIC 0xa0
+#define AMDVI_SB_IOAPIC_ID 0xa0
#define AMDVI_LOCAL_APIC_ADDR 0xfee00000
Introduce AMD IOMMU interrupt remapping and hook it onto the existing interrupt remapping infrastructure Signed-off-by: David Kiarie <davidkiarie4@gmail.com> --- hw/i386/amd_iommu.c | 206 +++++++++++++++++++++++++++++++++++++++++++++++++++- hw/i386/amd_iommu.h | 2 +- 2 files changed, 206 insertions(+), 2 deletions(-)