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[85.180.218.25]) by smtp.gmail.com with ESMTPSA id h7sm8423363wmg.24.2016.10.01.03.07.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 01 Oct 2016 03:07:05 -0700 (PDT) From: Artyom Tarasenko To: qemu-devel@nongnu.org Date: Sat, 1 Oct 2016 12:05:07 +0200 Message-Id: <1475316333-9776-4-git-send-email-atar4qemu@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1475316333-9776-1-git-send-email-atar4qemu@gmail.com> References: <1475316333-9776-1-git-send-email-atar4qemu@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [PATCH 03/29] target-sparc: add UA2005 TTE bit #defines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , Artyom Tarasenko , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Artyom Tarasenko --- target-sparc/cpu.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 238ebf2..2c169e1 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -290,11 +290,17 @@ enum { #define TTE_VALID_BIT (1ULL << 63) #define TTE_NFO_BIT (1ULL << 60) +#define TTE_NFO_BIT_UA2005 (1ULL << 62) #define TTE_USED_BIT (1ULL << 41) +#define TTE_USED_BIT_UA2005 (1ULL << 47) #define TTE_LOCKED_BIT (1ULL << 6) +#define TTE_LOCKED_BIT_UA2005 (1ULL << 61) #define TTE_SIDEEFFECT_BIT (1ULL << 3) +#define TTE_SIDEEFFECT_BIT_UA2005 (1ULL << 11) #define TTE_PRIV_BIT (1ULL << 2) +#define TTE_PRIV_BIT_UA2005 (1ULL << 8) #define TTE_W_OK_BIT (1ULL << 1) +#define TTE_W_OK_BIT_UA2005 (1ULL << 6) #define TTE_GLOBAL_BIT (1ULL << 0) #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT) @@ -302,14 +308,24 @@ enum { #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT) #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT) #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT) +#define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005) #define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT) #define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT) + +#define TTE_IS_NFO_UA2005(tte) ((tte) & TTE_NFO_BIT_UA2005) +#define TTE_IS_USED_UA2005(tte) ((tte) & TTE_USED_BIT_UA2005) +#define TTE_IS_LOCKED_UA2005(tte) ((tte) & TTE_LOCKED_BIT_UA2005) +#define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005) +#define TTE_IS_PRIV_UA2005(tte) ((tte) & TTE_PRIV_BIT_UA2005) +#define TTE_IS_W_OK_UA2005(tte) ((tte) & TTE_W_OK_BIT_UA2005) + #define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT) #define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT) #define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT) #define TTE_PGSIZE(tte) (((tte) >> 61) & 3ULL) +#define TTE_PGSIZE_UA2005(tte) ((tte) & 7ULL) #define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL) #define SFSR_NF_BIT (1ULL << 24) /* JPS1 NoFault */