| Message ID | 1475316333-9776-6-git-send-email-atar4qemu@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 10/01/2016 05:05 AM, Artyom Tarasenko wrote: > As described in Chapter 5.7.6 of the UltraSPARC Architecture 2005, > outstanding disrupting exceptions that are destined for privileged mode can only > cause a trap when the virtual processor is in nonprivileged or privileged mode and > PSTATE.ie = 1. At all other times, they are held pending. > > Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> > --- > target-sparc/cpu.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson <rth@twiddle.net> r~
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index bafa8d9..ff2e053 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -716,8 +716,9 @@ static inline int cpu_interrupts_enabled(CPUSPARCState *env1) if (env1->psret != 0) return 1; #else - if (env1->pstate & PS_IE) + if ((env1->pstate & PS_IE) && !cpu_hypervisor_mode(env1)) { return 1; + } #endif return 0;
As described in Chapter 5.7.6 of the UltraSPARC Architecture 2005, outstanding disrupting exceptions that are destined for privileged mode can only cause a trap when the virtual processor is in nonprivileged or privileged mode and PSTATE.ie = 1. At all other times, they are held pending. Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> --- target-sparc/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)