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Ip=[131.228.2.241]; Helo=[fihe3nok0735.emea.nsn-net.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR07MB1440 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.2.109 Subject: [Qemu-devel] [PATCH] nvic: allow to set pending status for not active interrupts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, rfsw-patches@mlist.nokia.com, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Marcin Krzeminski According to ARM DUI 0552A 4.2.10. NVIC set pending status also for disabled interrupts. This patch adds possibility to emulate this in Qemu. Signed-off-by: Marcin Krzeminski --- hw/intc/arm_gic.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index b30cc91..85be6e4 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -147,7 +147,8 @@ static void gic_set_irq_11mpcore(GICState *s, int irq, int level, { if (level) { GIC_SET_LEVEL(irq, cm); - if (GIC_TEST_EDGE_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) { + if (GIC_TEST_EDGE_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm) + || (!GIC_TEST_ACTIVE(irq, cm) && s->revision == REV_NVIC)) { DPRINTF("Set %d pending mask %x\n", irq, target); GIC_SET_PENDING(irq, target); }