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Sat, 15 Oct 2016 20:38:39 -0700 (PDT) Received: from bigtime.com ([2607:fb90:848f:44ba:5e51:4fff:fe40:9c64]) by smtp.gmail.com with ESMTPSA id v186sm11672982qkb.23.2016.10.15.20.38.37 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Oct 2016 20:38:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 15 Oct 2016 20:37:41 -0700 Message-Id: <1476589070-5792-7-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1476589070-5792-1-git-send-email-rth@twiddle.net> References: <1476589070-5792-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400d:c09::244 Subject: [Qemu-devel] [PATCH 06/15] tcg/i386: Implement field extraction opcodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 9 ++++++--- tcg/i386/tcg-target.inc.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 3 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 7625188..302ca96 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -94,8 +94,8 @@ extern bool have_bmi1; #define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nor_i32 0 #define TCG_TARGET_HAS_deposit_i32 1 -#define TCG_TARGET_HAS_extract_i32 0 -#define TCG_TARGET_HAS_sextract_i32 0 +#define TCG_TARGET_HAS_extract_i32 1 +#define TCG_TARGET_HAS_sextract_i32 1 #define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_add2_i32 1 #define TCG_TARGET_HAS_sub2_i32 1 @@ -126,7 +126,7 @@ extern bool have_bmi1; #define TCG_TARGET_HAS_nand_i64 0 #define TCG_TARGET_HAS_nor_i64 0 #define TCG_TARGET_HAS_deposit_i64 1 -#define TCG_TARGET_HAS_extract_i64 0 +#define TCG_TARGET_HAS_extract_i64 1 #define TCG_TARGET_HAS_sextract_i64 0 #define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_add2_i64 1 @@ -142,6 +142,9 @@ extern bool have_bmi1; ((ofs) == 0 && (len) == 16)) #define TCG_TARGET_deposit_i64_valid TCG_TARGET_deposit_i32_valid +#define TCG_TARGET_extract_i32_valid(ofs, len) ((ofs) == 8 && (len) == 8) +#define TCG_TARGET_extract_i64_valid TCG_TARGET_extract_i32_valid + #if TCG_TARGET_REG_BITS == 64 # define TCG_AREG0 TCG_REG_R14 #else diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index eeb1777..091c6ff 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -2143,6 +2143,32 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; + OP_32_64(extract): + /* Note that TCG_TARGET_extract_*_valid only allows pos=8, len=8, + on the off-chance that we can use the high-byte registers. + Otherwise we emit the same ext16 + shift pattern that we would + have gotten from the normal tcg-op.c expansion. */ + if (args[1] < 4 && args[0] < 8) { + /* Do not set P_REXB_RM, so that we do get the %[abcd]h regs. */ + tcg_out_modrm(s, OPC_MOVZBL, args[0], args[1] + 4); + } else { + tcg_out_ext16u(s, args[0], args[1]); + tcg_out_shifti(s, SHIFT_SHR, args[0], 8); + } + break; + + case INDEX_op_sextract_i32: + /* Note that we don't implement sextract_i64, as we cannot + sign-extend to 64-bits without using the REX prefix that + explicitly excludes access to the high-byte registers. */ + if (args[1] < 4 && args[0] < 8) { + tcg_out_modrm(s, OPC_MOVSBL, args[0], args[1] + 4); + } else { + tcg_out_ext16s(s, args[0], args[1], 0); + tcg_out_shifti(s, SHIFT_SAR + rexw, args[0], args[0]); + } + break; + case INDEX_op_mb: tcg_out_mb(s, args[0]); break; @@ -2204,6 +2230,9 @@ static const TCGTargetOpDef x86_op_defs[] = { { INDEX_op_setcond_i32, { "q", "r", "ri" } }, { INDEX_op_deposit_i32, { "Q", "0", "Q" } }, + { INDEX_op_extract_i32, { "r", "r" } }, + { INDEX_op_sextract_i32, { "r", "r" } }, + { INDEX_op_movcond_i32, { "r", "r", "ri", "r", "0" } }, { INDEX_op_mulu2_i32, { "a", "d", "a", "r" } }, @@ -2265,6 +2294,7 @@ static const TCGTargetOpDef x86_op_defs[] = { { INDEX_op_extu_i32_i64, { "r", "r" } }, { INDEX_op_deposit_i64, { "Q", "0", "Q" } }, + { INDEX_op_extract_i64, { "r", "r" } }, { INDEX_op_movcond_i64, { "r", "r", "re", "r", "0" } }, { INDEX_op_mulu2_i64, { "a", "d", "a", "r" } },